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參數(shù)資料
| 型號： | MPC107 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁數(shù)： | 26/46頁 |
| 文件大?。?/td> | 585K |
| 代理商： | MPC107 |
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26
MPC107 Hardware Specifications (Rev 0.2)
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
Figure 15. I
2
C Timing Diagram IV (Qualified Signal)
1.4.3.5 EPIC Serial Interrupt Mode AC Timing SpeciTcations
Table 15 provides the EPIC serial interrupt mode AC timing speciTcations for the MPC107.
Notes:
1
See the MPC107 Users Manual for a description of the EPIC Interrupt Control Register (EICR)
describing S_CLK frequency programming.
S_RST, S_FRAME, and S_INT shown in Figure 16 and Figure 17 depict timing relationships to
sys_logic_clk and S_CLK and do not describe functional relationships between S_RST, S_FRAME, and
S_INT. See the MPC107 Users Manual for a complete description of the functional relationships
between these signals.
The sys_logic_clk waveform is the clocking signal of the internal peripheral logic from the output of the
peripheral logic PLL; sys_logic_clk is the same as SDRAM_SYNC_IN when the SDRAM_SYNC_OUT to
SDRAM_SYNC_IN feedback loop is implemented and the DLL is locked. See the MPC107 Users
Manual for a complete clocking description.
2
3
Table 15. EPIC Serial Interrupt Mode AC Timing Specifications
At recommended operating conditions (See Figure 2) with GVdd = 3.3 V ± 5% and LVdd = 3.3 V ± 5%
Num
Characteristic
Min
Max
Unit
Notes
1
S_CLK Frequency
1/14 SDRAM_SYNC_IN
1/2 SDRAM_SYNC_IN
MHz
1
2
S_CLK Duty Cycle
40
60
%
3
S_CLK Output Valid Time
D
TBD = x
nS
4
Output Hold Time
0
D
nS
5
S_FRAME, S_RST Output Valid
Time
D
1 sys_logic_clk period +
x
nS
2
6
S_INT Input Setup Time to
S_CLK
1 sys_logic_clk period +
TBD
D
nS
2
7
S_INT Inputs Invalid (Hold
Time) to S_CLK
D
0
nS
2
SCL/SDA
realtime
VM
SCL/SDA
qualified
VM
Delay
1
Notes:
1
The delay is the Local Memory clock times DFFSR times 2 plus 1 Local Memory clock.
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