參數(shù)資料
型號(hào)： MPC107
廠商： Motorola, Inc.
英文描述： 32-Bit Microprocessor(32位微處理器)
中文描述： 32位微處理器（32位微處理器）
文件頁(yè)數(shù)： 44/46頁(yè)
文件大?。?/td> 585K
代理商： MPC107
44
MPC107 Hardware Specifications (Rev 0.2)
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
Document Revision History
1.8 Document Revision History
Table 19 provides a revision history for this hardware speciTcation.
Table 19. Document Revision History
Document Revision
Substantive Change(s)
0
Preliminary release with some TBDs in the spec tables.
0.1
Removed references to CBGA packaging.
Removed references to BVdd = 2.5V and GVdd = 2.5V until device characterization is
complete.
Corrected òPower Supply Ramp Upó range in Figure 2 to show Vdd being stable
BEFORE 100 microsecond PLL Relock time.
ModiTed Table 4:
￥ Filled in current values from IBIS model.
￥ Changed òDRV_STDó to òDRV_CPUó and changed òOVddó to òBVddó.
Added Note 10 referencing power consumption on PLL supply voltage pins to Table 5.
Updated Table 6 PBGA package thermal characteristics.
Corrected DLL Lock Range (DLL_EXTEND=1) equation in Table 8.
ModiTed Figure 6 reducing T
loop
Propagation Delay Time from 40 ns to 15 ns.
ModiTed Figure 22 for PBGA packaging.
Updated Table 17, the tables notes, and the corresponding text in Section 1.7.5, òPull-
up/Pull-down Resistor Requirementsó
ModiTed Note 5 of Table 18 reducing maximum memory VCO frequency from 225 MHz
to 200 MHz. Updated the affected PLL_CFG[0-3] entries (0001 and 0010) in the table.
Revised Section 1.7.6, òThermal Management Informationó for PBGA packaging.
0.2
Lowered PCI Input Frequency (PCI_SYNC_IN) in Table 7 from 25 MHz to 12.5 MHz,
see Table 18 for speciTc details on applicability of lower input frequency.
ModiTed Table 8:
￥ Completed speciTcation numbering.
￥ Combined PCI_SYNC_IN jitter speciTcations, 7 and 8, into speciTcation 7.
￥ Added speciTcation 9d.
￥ Updated values for speciTcations 7, 9b, and 9c.
￥ Deleted OSC_IN Jitter (Cycle-to-Cycle) speciTcation.
￥ Added Note 8 to speciTcations 1a, 1b, 17, and 18; updated the òMinó part of these
speciTcations to correspond to the lower PCI 12.5 MHz input frequency.
Added Figure 5.
Replaced Input AC Timing TBDs in Table 9 with values.
Replaced Output AC Timing TBDs for speciTcations 12c, 12d, 12e, and 14a in Table 10
with values.
Replaced Figure 22 with Motorola standard packaging drawing for 503 pin PBGA.
Updated Table 18:
￥ Lowered input frequency on Refs 2 and C.
￥ Ref A changed to reserved.
￥ Ref 8 is changed to usable for 66 MHz devices.
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