參數(shù)資料
型號: MPC107
廠商: Motorola, Inc.
英文描述: 32-Bit Microprocessor(32位微處理器)
中文描述: 32位微處理器(32位微處理器)
文件頁數(shù): 3/46頁
文件大小: 585K
代理商: MPC107
MPC107 Hardware Specifications (Rev 0.2)
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
3
Overview
1.1 Overview
The MPC107 integrates a PCI bridge, memory controller, DMA controller, EPIC interrupt controller/timers,
a message unit with an Intelligent Input/Output (I
2
O) message controller, and an Inter-Integrated Circuit
(I
2
C) controller. The integration reduces the overall packaging requirements and the number of discrete
devices required for an embedded system.
Figure 1 shows the major functional units within the MPC107. Note that this is a conceptual block diagram
intended to show the basic features rather than an attempt to show how these features are physically
implemented.
Figure 1. MPC107 Block Diagram
60x Bus Interface (64- or 32-Bit Data Bus)
Address
Translator
DLL
Fanout
Buffers
PCI
Arbiter
Message
Unit
(with I
2
O)
I
2
C
Controller
CDMA
IEPIC
Controller
/Timers
PCI Bus
Interface Unit
Memory
Controller
Data Path
ECC Controller
Central
Control
Unit
32-Bit
OSC_IN
Five
Request/Grant
Pairs
I
2
C
5 IRQs/
16 Serial
Interrupts
Peripheral Logic Block
PLL
PCI Bus
Clocks
Data (64-Bit)
Address
(32-Bit)
Data Bus
(64- or 32-bit)
with 8-bit Parity
or ECC
Memory/ROM/
Port X Control/
Address
PCI Interface
Configuration
Registers
MPC107
PCI_SYNC_IN
SDRAM Clocks
CPU Clocks
SDRAM_SYNC_IN
Additional features:
¥ Programmable I/O
¥ with Watchpoint
¥ JTAG/COP Interface
¥ Power Management
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