參數(shù)資料
型號(hào)： MPC107
廠(chǎng)商： Motorola, Inc.
英文描述： 32-Bit Microprocessor(32位微處理器)
中文描述： 32位微處理器（32位微處理器）
文件頁(yè)數(shù)： 5/46頁(yè)
文件大?。?/td> 585K
代理商： MPC107
MPC107 Hardware Specifications (Rev 0.2)
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
5
Features
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Message unit
Two doorbell registers
An extended doorbell register mechanism that facilitates interprocessor communication
through interrupts in a dual-local-processor system
Two inbound and two outbound messaging registers
I
2
O message controller
I
2
C controller with full master/slave support (except broadcast all)
Embedded programmable interrupt controller (EPIC)
Five hardware interrupts (IRQs) or 16 serial interrupts
Four programmable timers
Integrated PCI bus, CPU, and SDRAM clock generation
Programmable PCI bus, 60x, and memory interface output drivers
Dynamic power managementSupports 60x nap, doze, sleep, and suspend modes
Programmable input and output signals with watchpoint capability
Built-in PCI bus performance monitor facility
Debug features
Error injection/capture on data path
IEEE 1149.1 (JTAG)/test interface
Processor interface
Supports up to two PowerPCa microprocessors with 60x bus interface
Supports various operating frequencies and bus divider ratios
32-bit address bus, 64/32-bit data bus supported at 100 MHz
Supports full memory coherency
Supports optional local bus slave
Decoupled address and data buses for pipelining of 60x accesses
Store gathering on 60x-to-PCI writes
Concurrent transactions on 60x and PCI buses supported
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