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參數(shù)資料
| 型號： | MPC107 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁數(shù)： | 41/46頁 |
| 文件大?。?/td> | 585K |
| 代理商： | MPC107 |
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MPC107 Hardware Specifications (Rev 0.2)
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
41
System Design Information
1.7.5 Pull-up/Pull-down Resistor Requirements
The data bus input receivers are normally turned off when no read operation is in progress; therefore, they
do not require pull-up resistors on the bus. The processor data bus signals are: DH[0D31], DL[0D31], and
DP[0D7]. The memory data bus signals are: MDH[0D31], MDL[0D31], and PAR/AR[0D7].
If the 32-bit data bus mode is selected, the input receivers of the unused data and parity bits (DL[0D31],
DP[4D7], MDL[0D31], and PAR[4D7]) will be disabled, and their outputs will drive logic zeros when they
would otherwise normally be driven. For this mode, these pins do not require pull-up resistors, and should
be left unconnected by the system to minimize possible output switching.
It is recommended that MTP[1D2] have weak pull-up resistors (2K D 10K Ohms) connected to GVdd.
It is recommended that the following signals be pulled up to OVdd with weak pull-up resistors (2K D 10K
Ohms): SDA, SCL, and FTP[2D3].
It is recommended that the following PCI control signals be pulled up to LVdd with weak pull-up resistors
(2K D 10K Ohms): DEVSEL, FRAME, IRDY, LOCK, PERR, SERR, STOP, and TRDY. The resistor values
may need to be adjusted stronger to reduce induced noise on speciTc board designs.
The following pins have internal pull-up resistors enabled at all times: REQ[0D4], TCK, TDI, TMS, TRST,
BR1, HRESET_CPU, MCP, QACK, SRESET, TEST and TRIG_OUT. See Table 17.MPC107 Pinout
Listing for more information.
The following pins have internal pull-up resistors enabled only while device is in the reset state: MDL0,
FOE, RCS0, SDRAS, SDCAS, CKE, SDBAO, and SDMA[10D1]. See Table 17.MPC107 Pinout Listing for
more information.
The following pins are reset conTguration pins: MDL0, FOE, RCS0, SDBAO, SDMA[10D1], and
PLL_CFG[0D3]. These pins are sampled during reset to conTgure the device.
Any other unused active low input pins should be tied to a logic one level via weak pull-up resistors (2K D
10K Ohms) to the appropriate power supply listed in Figure 17. Unused active high input pins should be
tied to GND via weak pull-down resistors (2K D 10K Ohms).
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