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參數(shù)資料
| 型號： | MPC107 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁數(shù)： | 22/46頁 |
| 文件大?。?/td> | 585K |
| 代理商： | MPC107 |
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22
MPC107 Hardware Specifications (Rev 0.2)
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
1.4.3.4 I
2
C AC Timing SpeciTcations
Table 12 provides the I
2
C input AC timing speciTcations for the MPC107.
Notes:
1
2
Units for these speciTcations are in SDRAM_CLK/CPU_CLK units.
The actual values depend on the setting of the Digital Filter Frequency Sampling Rate (DFFSR) bits in the
Frequency Divider Register I2CFDR. Therefore, the noted timings in the above table are all relative to quali-
Ted signals. The qualiTed SCL and SDA are delayed signals from what is seen in real time on the I
C bus.
The qualiTed SCL, SDA signals are delayed by the SDRAM_CLK/CPU_CLK clock times DFFSR times 2 plus
1 SDRAM_CLK/CPU_CLK clock. The resulting delay value is added to the value in the table (where this note
is referenced). See Figure 13.
Timing is relative to the Sampling Clock (not SCL).
FDR[x] refers to the Frequency Divider Register I2CFDR bit x.
Input clock low and high periods in combination with the FDR value in the Frequency Divider Register
(I2CFDR) determine the maximum I
C input frequency. See Figure 13.
3
4
5
Table 12. I
2
C Input AC Timing Specifications
At recommended operating conditions (See Figure 2) with GVdd = 3.3 V ± 5% and LVdd = 3.3 V ± 5%
Num
Characteristic
Min
Max
Unit
Notes
1
Start condition hold time
4.0
CLKs
1,2
2
Clock low period
(The time before MPC107 will drive
SCL low as a transmitting slave
after detecting SCL low as driven by
an external master.)
8.0 + (16 x 2
FDR[4:2]
) x (5 -
4({FDR[5],FDR[1]} == b10) -
3({FDR[5],FDR[1]} == b11) -
2({FDR[5],FDR[1]} == b00) -
1({FDR[5],FDR[1]} == b01))
CLKs
1,2,4, 5
3
SCL/SDA rise time (from 0.5v to
2.4v)
1
mS
4
Data hold time
0
nS
2
5
SCL/SDA fall time (from 2.4 to 0.5v)
1
mS
6
Clock high period
(Time needed to either receive a
data bit or generate a START or
STOP.)
5.0
CLKs
1,2, 5
7
Data setup time
3.0
ns
3
8
Start condition setup time (for
repeated start condition only)
4.0
CLKs
1,2
9
Stop condition setup time
4.0
CLKs
1,2
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