參數(shù)資料
型號: MPC107
廠商: Motorola, Inc.
英文描述: 32-Bit Microprocessor(32位微處理器)
中文描述: 32位微處理器(32位微處理器)
文件頁數(shù): 13/46頁
文件大小: 585K
代理商: MPC107
MPC107 Hardware Specifications (Rev 0.2)
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
13
Electrical and Thermal Characteristics
1.4.2 Thermal Characteristics
Table 6 provides the package thermal characteristics for the MPC107.
1.4.3 AC Electrical Characteristics
This section provides the AC electrical characteristics for the MPC107. After fabrication, functional parts
are sorted by maximum core frequency as shown in Table 7 and Section 1.4.3.1, òClock AC SpeciTcationsó
and tested for conformance to the AC speciTcations for that frequency. The core frequency is determined by
the bus (PCI_SYNC_IN) clock frequency and the settings of the PLL_CFG[0D3] signals. Parts are sold by
maximum processor core frequency; see Section 1.9, òOrdering Informationó.
Table 7 provides the operating frequency information for the MPC107.
Table 6. PBGA Package Thermal Characteristics
Characteristic
Symbols
Value
Units
Die Junction-to-Case Thermal Resistance
q
JC
< 0.1
C/W
Die Junction-to-Board Thermal Resistance
q
JB
5.2
C/W
Package Junction-to-Ambient Thermal Resistance
2
q
JA
See Figure 25
Notes:
1. Refer to Section 1.7, òSystem Design Informationó for more details about thermal
management
.
2. T
J
= T
A
+ P
D
x
q
JA
T
J
= Die junction temperature.
T
A
= System air ambient temperature near the package.
P
D
= Average power consumed by IC in Watts.
q
JA
= Thermal resistance from die junction to ambient air in C/W
Table 7. Operating Frequency
At recommended operating conditions (See Table 2) with GVdd = 3.3 V ± 5% and LVdd = 3.3 V ± 5%
Characteristic
1
66 MHz
100 MHz
Units
Min
Max
Min
Max
Core (memory bus/processor bus) frequency
25
66
25
100
MHz
PCI input frequency (PCI_SYNC_IN)
12.5D66
MHz
Notes:
Caution: The PCI_SYNC_IN frequency and PLL_CFG[0D3] settings must be chosen such that the resulting
peripheral logic/ memory bus frequency, CPU (core) frequency, and PLL (VCO) frequencies do not exceed
their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0D3] signal description
in Section 1.6, òPLL ConTgurationó for valid PLL_CFG[0D3] settings and PCI_SYNC_IN frequencies.
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