- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371014 > MC145230 (Motorola, Inc.) Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器) PDF資料下載
參數(shù)資料
| 型號(hào)： | MC145230 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器) |
| 中文描述： | 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 9/71頁 |
| 文件大?。?/td> | 906K |
| 代理商： | MC145230 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當(dāng)前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁
MC145225 MC145230
9
MOTOROLA RF/IF DEVICE DATA
4. DEVICE OVERVIEW
Refer to the Block Diagram in Section 1.
4A. SERIAL INTERFACE AND REGISTERS
The serial interface is comprised of a Clock pin (Clk), a
Data In pin (Din), and an Enable pin (Enb). Information on the
data input pin is shifted into a shift register on the low–to–high
transition of the serial clock. The data format is most
significant bit (MSB) first. Both Clk and Enb are
Schmitt–triggered inputs.
The R and N registers contain counter divide ratios for the
main loop, PLL. The R and N registers contain counter
divide ratios for the secondary loop, PLL . Additional contol
bits are located in the R , N, and C registers. The D register
controls the digital–to–analog converters (DACs). Random
access is allowed to the N, R , Hr, Hn , D, and C registers.
Two 16–bit holding registers, Hr and Hn , feed registers R
and N , respectively. The R and N registers determine the
divide ratios of the R and N counters, respectively. Thus, the
information presented to the R and N counters is
double–buffered. Using the proper programming sequence,
new divide ratios may be presented to the N, R, and N
counters; simultaneously.
Enb is used to activate the data port and allow transfer of
data. To ensure that data is accepted by the device, the Enb
signal line must initially be a high voltage (not asserted), then
make a transition to a low voltage (asserted) prior to the
occurrence of a serial clock, and must remain asserted until
after the last serial clock of the burst. Serial data may be
transferred in an SPI format (while Enb remains asserted).
Data is transferred to the appropriate register on the rising
edge of Enb (see Table 1). “Short shifting”, depicted as
BitGrabber
in the table, allows access to certain registers
without requiring address bits. When Enb is inactive (high),
Clk is inhibited from shifting the shift register.
The serial input pins may NOT be driven above the supply
voltage applied to the Vpos pins.
4B. REFERENCE INPUT AND COUNTERS CIRCUITS
Reference (Oscillator) Circuit
For the Colpitts reference oscillator, one pin ties to the
base (Oscb, pin 32) and the other ties to the emitter (Osce,
pin 1), of an on–chip NPN transistor. In addition, the
reference circuit may be operated in the external reference
(XRef) mode as selectable via bit C6 when the Mode pin is
high.
The Oscb and Osce pins support an external fundamental
or overtone crystal. The output of the oscillator is routed to
both the reference counter for the main loop (R counter) and
the reference counter for the secondary loop (R counter).
In a second mode, determined by bit C6 being 1 and the
Mode pin being high, Osce is an input which accepts an
ac–coupled signal from a TCXO or other source. Oscb must
be floated. If the Mode pin is low, this “XRef mode” is not
allowed.
Reference Counter for Main Loop
Main reference counter R divides down the frequency at
Osce and feeds the phase/frequency detector for the main
loop. The detector feeds the two charge pumps with outputs
PDout–Hi and PDout–Lo. The division ratio of the R counter is
determined by bits in the R register.
Reference Counter for Secondary Loop
Secondary reference counter R divides down the
frequency at Osce and feeds the phase/frequency detector
for the secondary loop. The detector output is PDout. The
division ratio of the R counter is determined by the 16 LSBs
of the R register.
The R counter has a special mode to provide a frequency
output at pins fout and fout (differential outputs). These are
low–jitter ECL–type outputs. With the Mode pin low, software
control allows the Osce frequency to be divided–by–8, –10,
or –12.5 and routed to the fout pins. This output is derived by
tapping off of a front–end stage of the R counter and feeding
the auxiliary counter which provides the divided–down
frequency. The chip must have the Mode pin low, which
activates the fout pins. The actual R divide ratio must be
divisible by 2 or 2.5 when the fout pins are activated. There is
no such restriction when the Mode pin is high. See
Section 6D,
R
Register.
4C. LOOP DIVIDER INPUTS AND COUNTER CIRCUITS
fin Inputs and Counter Circuit
fin and fin are high–frequency inputs to the amplifier which
feeds the N counter. A small signal can feed these inputs
either differentially or single–ended.
The N counter divides down the external VCO frequency
for the main loop. (The divide ratio of the N counter is also
known as the loop multiplying factor.) The divide ratio of this
counter is determined by the 18 LSBs of the N register. The
output of the N counter feeds the phase/frequency detector
for the main loop.
fin Input and Counter Circuit
fin is the high–frequency input to the amplifier which feeds
the N counter. A small signal can feed this input
single–ended.
The N counter divides down the external VCO frequency
for the secondary loop. (The divide ratio of the N counter is
also known as the loop multiplying factor.) The divide ratio of
this counter is determined by bits in the N register. The
output of the N counter feeds the phase/frequency detector
for the secondary loop.
4D. VOLTAGE MULTIPLIER AND KEEP–ALIVE
CIRCUITS
The voltage multiplier produces approximately two times
the voltage present at the Vpos pins over a supply range of
1.8 V to about 2.5 V. With a supply range of approximately
2.5 V to 3.6 V, the elevated voltage is regulated/limited to
approximately 5 V. The elevated voltage, present at the Cmult
pin, is applied to both phase detectors. An external capacitor
to Gnd is required on the Cmult pin. The other capacitors
required for the multiplier are on–chip.
A capacitor to Gnd is also required on the Creg pin. The
voltage on this pin is equal to the voltage on the Vpos pins
over a supply range of 1.8 V to about 2.5 V. The voltage on
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC14528BCL | Dual Monostable Multivibrator |
| MC14528 | DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| MC14528 | Dual Monostable Multivibrator |
| MC14528BFEL | Dual Monostable Multivibrator |
| MC14528BCP | Dual Monostable Multivibrator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC14526B AC7 WAF | 制造商:ON Semiconductor 功能描述: |
| MC14526BAC7 WAF | 制造商:ON Semiconductor 功能描述: |
| MC14526BCL | 制造商: 功能描述: 制造商:undefined 功能描述: |
| MC14526BCP | 功能描述:計(jì)數(shù)器移位寄存器 3-18V Presettable RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC14526BCPG | 功能描述:計(jì)數(shù)器移位寄存器 3-18V Presettable 4-Bit Down RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。