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| 型號(hào)： | MC145230 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器) |
| 中文描述： | 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 61/71頁 |
| 文件大?。?/td> | 906K |
| 代理商： | MC145230 |
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MC145225 MC145230
61
MOTOROLA RF/IF DEVICE DATA
Don’t Care
Nibble
(Shifted in First)
Least
Significant Nibble
(Shifted in Last)
0
N REGISTER
Conventional Access
0
1
0
Most Significant
Nibble
(Shifted in First)
Control
LD
Window
Phase Detector
Program
MSB of N Counter
Divide Value
Current
Ratio
Least
Significant Nibble
(Shifted in Last)
8A.
QUICK REFERENCE (continued)
Address Nibble
Control = Control for Auxiliary Divider
See Table A
LD Window = Lock Detector Window for Main Loop
0 = 32 Osce periods
1 = 128 Osce periods
Phase Detector Program = Detector Program for Main Loop
See Table B
Current Ratio = PDout–Hi to PDout–Lo Current Ratio
0 = 4:1
1 = 8:1
LSB of N Counter
Divide Value
EXAMPLE:
To program the N counter to divide by 1000 in decimal, first convert to hexadecimal: $3E8. Then, add leading 0s to form
2 leading bits plus 2 bytes (2 bits plus 4 nibbles); this is N17 to N0. Bits N23 to N18 should be appropriate to control the
above functions. Finally, load the N register. Loading the N register also causes data to pass from the Hr register to the
R register and data from the Hn
′
register to pass to the N
′
register.
With BitGrabber, no address bits are needed. With a conventional load, address bits A3 to A0 must be included.
A3
A2
A1
A0
x
x
x
x
N23
. . .
N20
N19
. . .
N16
N15
. . .
N12
N11
. . .
N8
N7
. . .
N4
N3
. . .
N0
N3
. . .
N0
N7
. . .
N4
N11
. . .
N8
N15
. . .
N12
N19 N18 N17 N16
N23 N22 N21 N20
BitGrabber Access
See Below
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Mode = Low
R 1
R 0
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NOTE:
When the Mode pin is high, the fout pins are configured
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PDout–Hi enabled and PDout–Lo floating
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