參數(shù)資料
型號： MC145230
廠商： Motorola, Inc.
英文描述： Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器)
中文描述： 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙鎖相環(huán)頻率合成器）
文件頁數(shù)： 5/71頁
文件大?。?/td> 906K
代理商： MC145230
MC145225 MC145230
5
MOTOROLA RF/IF DEVICE DATA
3B. DC ELECTRICAL CHARACTERISTICS
Vpos = 1.8 to 3.6 V, Voltages Referenced to Gnd, TA = –40 to 85
°
C, unless otherwise statedt
Parameter
Condition
Symbol
Guaranteed
Limit
Unit
Maximum Low–Level Input Voltage
(Din, Clk, Enb, Mode, fout/Pol , fout/Pol)
fout/Pol and fout/Pol Configured as Inputs
VIL
0.3 x Vpos
V
Minimum High–Level Input Voltage
(Din, Clk, Enb, Mode, fout/Pol , fout/Pol)
fout/Pol and fout/Pol Configured as Inputs
VIH
0.7 x Vpos
V
Minimum Hysteresis Voltage
(Clk)
VHys
VOL
100
mV
Maximum Low–Level Output Voltage
(LD, Output A, Output B)
Iout = 20
μ
A
0.1
V
Minimum High–Level Output Voltage
(LD, Output A, Output B)
Iout = –20
μ
A
VOH
Vpos – 0.1
V
Minimum Low–Level Output Current
(LD, Output A, Output B)
Vout = 0.3 V
IOL
0.7
mA
Minimum High–Level Output Current
(LD, Output A, Output B)
Vout = Vpos – 0.3 V
IOH
–0.7
mA
Minimum Low–Level Output Current
(Output C)
Vout = 0.2 V
Vin = Vpos or Gnd; fout/Pol and fout/Pol
Configured as Inputs
IOL
Iin
2.8
mA
Maximum Input Leakage Current
(Din, Clk, Enb, Mode, fout/Pol , fout/Pol)
±
1.0
μ
A
Maximum Output Leakage Current
(Output B, Output C)
Vout = Vpos or Gnd; Output in High–Impedance
State
IOZ
±
1
μ
A
Maximum ON Resistance
(Output C)
1.8 V
≤
Vpos < 2.5 V Supply
2.5 V
≤
Vpos
≤
3.6 V Supply
Vin = Vpos or Gnd; Outputs Open; Both PLLs in
Standby Mode; Oscillator in Standby Mode;
DAC1 and DAC2 Output = Zero; Keep–alive
Oscillator Off (Notes 1, 2, and 3)
Ron
75
50
Maximum Standby Supply Current
(Vpos and DAC Vpos Tied Together)
ISTBY
10
μ
A
NOTES:
1. The total supply current drain for the keep–alive oscillator, voltage multiplier, and regulator is approximately 250
μ
A.
2. When the Mode pin is tied high, bit C6 must be programmed to a 0 for minimum supply current drain. Otherwise, if C6 = 1, the current drain is approximately
8
μ
A for a 1.8 V supply and approximately 40
μ
A for a 3.6 V supply. This restriction on bit C6 does not apply when the Mode pin is tied low.
3. To ensure minimum standby supply current drain, the voltage potential at the Cmult pin must not be allowed to fall below the potential at the Vpos pins.
See discussion in Section 5E under
Cmult
.
3C. PDout–Hi AND PDout–Lo PHASE/FREQUENCY DETECTOR CHARACTERISTICS
Nominal Output Current, Vpos = 1.8 V: PDout–Hi = 2.8 mA, PDout–Lo = 0.7 or 0.35 mA
Nominal Output Current, Vpos
≥
2.5 V: PDout–Hi = 4.4 mA, PDout–Lo = 1.1 or 0.55 mA
Rx = 2.0 k
, Voltages Referenced to Gnd, Voltage Multiplier ON, TA = –40 to 85
°
C
Parameter
Condition
Guaranteed
Limit
Unit
Maximum Source Current Variation Part–to–Part
(See Note)
Vout = 0.5 x VCmult
Vout = 0.5 x VCmult
Iout Variation
≤
27%
Vout = 0 or VCmult
±
14
%
Maximum Sink–versus–Source Mismatch
(See Note)
20
%
Output Voltage Range
(See Note)
0.6 to VCmult – 0.6 V
±
50
V
Maximum Three–State Leakage Current
nA
NOTE:
Percentages calculated using the following formula: (Maximum Value – Minimum Value)/Maximum Value.
3D. PDout PHASE/FREQUENCY DETECTOR CHARACTERISTICS
Vpos = 1.8 to 3.6 V, Voltages Referenced to Gnd, Voltage Multiplier ON, TA = –40 to 85
°
C
Parameter
Condition
Guaranteed
Limit
Unit
Minimum Low–Level Output Current
Vout = 0.3 V
Vout = VCmult – 0.3 V
Vout = 0 or VCmult
0.3
mA
Minimum High–Level Output Current
–0.3
mA
Maximum Three–State Leakage Current
±
50
nA
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