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參數(shù)資料
| 型號： | MC145230 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器) |
| 中文描述： | 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 46/71頁 |
| 文件大?。?/td> | 906K |
| 代理商： | MC145230 |
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MC145225 MC145230
46
MOTOROLA RF/IF DEVICE DATA
Figure 49. Sybil EVK Reference Spur Measurements
–10
–20
–30
–40
–110
–50
–60
–70
–80
–90
–100
Center 737.5000009 MHz
Span 64 kHz
1AVG
1SA
10
–0
6.4 kHz
25.00000000 MHz
10 dBm
Ref Lvl
– 73.32 dB
SWT
130 ms
Unit
dBm
1
1
It should be noted that the reference spur values obtained
from the simulation are lower than the values obtained from
the actual EVK. This is because the simulation model is an
“ideal” modeling of the PLL. To obtain results closer to the
actual implementation, the models should be “massaged” to
be more representative of the actual circuit. For example,
spur levels more consistent with actual circuitry can be
obtained by adding a resistance to ground at the input of the
VCO to represent leakage. The value chosen should be
consistent with VCO and circuit component performance.
To reduce simulation time, the H value may be used. By
reducing the frequency of the VCO output, the number of
samples required for simulation can also be reduced. The
output shown in Figure 50 shows the result of dividing the
VCO output of 730 MHz by 7.3 to produce a 100 MHz output.
The reference spurs are better represented since adequate
simulation time is possible.
To generate these outputs, the parameter values used
were those shown on the top level schematic. The simulator
was set to run a transient sweep, with td set for a delay that
would prevent the 4X frequency from being started. The initial
conditions were set to 1 V and the simulation run for 1 ms.
VCO was monitored and the probe display button FFT was
initiated. The X and Y axis were adjusted to those shown.
Note: These simulations are presented as the result of
“ideal” models and may not accurately display real hardware.
It would be best to load the VCO input with additional leakage
devices such as a large resistance, to accurately display real
conditions. These models are starting points for more
accurate implementations.
Loop filter analysis is more accurate, since the
predominate factors are in the loop filter itself. To simulate the
performance of the loop filter, td is set for 0, N is set to the
desired divider value, and Sz is set to the desired step. For
this example, 733 MHz was chosen.
NOTE
These values are for reference only. The
maximum operating frequency of the MC145181
is 550 MHz. For VCO frequencies greater than
550 MHz, an added external divider such as a
prescaler is necessary.
With the VCO model shown, V(ctrl) = 0 produces an output
of 727.6 MHz and at V(ctrl) = 1.35 V, the VCO frequency
would be 733 MHz; the minimum MC145230EVK default
operating frequency. To show the response of the loop filter to
a 10 MHz step at this operating frequency, Sz = 10 MHz/
25 kHz = 400. The simulation is run for 1 ms with a step
ceiling of 100 ns. The result is shown in Figure 51.
If the simulation is examined over a longer period of time,
the long term settling can be compared to the performance of
the actual circuitry. The plot shown in Figure 52 shows the
VCO control voltage with the display resolution set to 1 mV.
This compares to the plot of frequency variation
measurements made on the actual EVK. This plot is shown in
Figure 53.
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