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參數(shù)資料
| 型號： | MC145230 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器) |
| 中文描述： | 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 23/71頁 |
| 文件大?。?/td> | 906K |
| 代理商： | MC145230 |
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MC145225 MC145230
23
MOTOROLA RF/IF DEVICE DATA
R REGISTER BITS
See Figure 16 for R register access and serial data
format.
Y Coefficient (R 23 and R 22)
These bits are programmed per Table 18. Note that for the
MC145181, the bits are always programmed as 00. For
compatibility, the other combinations are reserved for use
with the MC145225 and MC145230.
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Output A Function (R 21 and R 20)
These bits control the function of the Output A pin per
Table 19. When selected as a general–purpose output, bit C7
controls the state of the pin. The signals fR and fR are the
outputs of the R and R counters, respectively. The selection
as a detector pulse is a test feature.
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Maximum Allowed
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Table 19. Output A Function Selection
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R 20
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for Output A
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0
0
General–Purpose Output
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0
1
fR
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1
0
fR
Phase/Frequency Detector
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1
1
V–Mult Control (R 19, R 18, R 17)
These bits control the voltage multiplier per Table 20.
When the multiplier is in the active state, the bits determine
the voltage multiplier’s refresh rate of the capacitor tied to the
Cmult pin.
When active, the bits should be programmed for the
lowest possible maximum frequency shown in the table. This
ensures that the voltage multiplier is operating at optimum
efficiency. For example, for a system utilizing a 16.8 MHz
reference, bits R 19, R 18, and R 17 should be programmed
as 001 if the user desires to use the voltage multiplier. If the
user does not want to use the multiplier, the bits should be
programmed as 000. In the latter case, only a 0.1
μ
F bypass
capacitor is needed at the Cmult pin and an external
phase/frequency detector supply voltage of 3.6 to 5.25 V
must be provided to the Cmult pin.
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R 19
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R 18
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R 17
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Multiplier
State
Inactive
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Frequency at
Osce Pin
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80 MHz
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0
0
0
0
0
1
Active
20 MHz
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Active
40 MHz
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Active
80 MHz
1
X
X
—
(for factory evaluation)
Test/Rst (R 16)
This bit must be programmed to 0 by the user.
R Counter Divide Ratio (R 15 to R 0)
These bits control the R counter divide ratio. Thus, these
bits determine the secondary loop’s minimum step size. This
step size is the same as the phase/frequency detector’s
operating frequency which must not exceed 600 kHz.
With the Mode pin tied high, the minimum allowed value is
20. The maximum value is 32,767.5. For ease of
programming, binary representation is used. However, the
binary value must be multiplied by 2. For example, if a divide
ratio of 1000 is needed, the 1000 in decimal is converted to
binary 0000 0011 1110 1000. This value is multiplied by 2
and becomes 0000 0111 1101 0000 and is loaded into the
device for R 15 to R 0. See Figure 16.
With the Mode pin tied low, Table 21 shows the divide
ratios available. There are two formulas for the divide ratio
when Mode is low.
If R 1 R 0 are 00: R Ratio = (Value of R 15 to R 2) x 2.
If R 1 R 0 are 01, 10, 11: R Ratio = (Value of R 15 to R 2)
x 2.5.
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