參數(shù)資料
型號(hào): MC145230
廠商: Motorola, Inc.
英文描述: Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器)
中文描述: 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器(帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙鎖相環(huán)頻率合成器)
文件頁(yè)數(shù): 3/71頁(yè)
文件大小: 906K
代理商: MC145230
MC145225 MC145230
3
MOTOROLA RF/IF DEVICE DATA
Clk
fin
fin
Enb
C Register
8 Bits
Output A
Mux
Output C
Output A
PDout–Hi
16
9
19
Power Connections:
Pin 2 = DAC Vpos
Pins 11, 24, 26, and 29 = Vpos
Pins 14, 15, 18, and 31 = Gnd
Output B
25
Din
Phase/
Frequency
Detector,
Timer,
and Control
Out C
Out B/Ref
Out A
Function
High–
current
Charge
Pump
Timer
Ph Det Pulse
fR
fR
PLL Stby
PLL Stby
PD Float
PD Float
Osc Stby
Low–
current
Charge
Pump
N Register
24 Bits
N Counter
18 Stages
3
fV
R Counter
16 Stages
fR
16
R Register
16 Bits
16
Hr Register
16 Bits
3
R Register
24 Bits
16
R Counter
16 Stages
N Counter
16 Stages
16
N Register
16 Bits
16
Hn Register
16 Bits
D Register
16 Bits
Shift Register and
Address Generator
5
6
7
18
+
12
13
Amp
Lo–I Gain
Polarity
PLL Stby
Oscillator
Osce
Oscb
1
32
Rx
17
PDout–Lo
20
Lock
Detector
Voltage
Multiplier
and Regulator
Cmult
Creg
21
22
LD
8
Lock
Detector
Window
V–Mult
Control
Phase/
Frequency
Detector
fV
fR
PDout
23
Supply Current
Minimization
Circuit
2
2
Test
Polarity
Ratio
10
Mode
fin
30
Amp
8
8
Auxiliary
Divider
3 Stages
fout/Pol
fout/Pol
28
27
DAC
8 Bits
DAC1
3
DAC
8 Bits
DAC2
4
DAC Vpos
2
1. BLOCK DIAGRAM
Osc
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