參數(shù)資料
型號(hào)： MC145230
廠商： Motorola, Inc.
英文描述： Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器)
中文描述： 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙鎖相環(huán)頻率合成器）
文件頁(yè)數(shù)： 12/71頁(yè)
文件大?。?/td> 906K
代理商： MC145230
MC145225 MC145230
12
MOTOROLA RF/IF DEVICE DATA
Table 2. Output A Configuration
Bit
R 20
C7
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Mode
Pin 10 — Mode Input
When the Mode pin is tied low (approximately Gnd), the
pair of pins named fout/Pol and fout/Pol become outputs fout
and fout. As such, these pins are the divided down reference
frequency. The division ratio is controlled by bits per Table 6.
In addition, when Mode is low, the R counter is preceded by
a fixed–divide prescaler. Also, only a crystal may be used at
pins Oscb and Osce; an external reference, such as a TCXO,
should not be used to drive either pin. The default on the
phase detector polarity is positive. See the summary in
Table 3.
When the Mode pin is tied high (approximately Vpos), the
pair of pins named fout/Pol and fout/Pol become inputs Pol
and Pol. As such, these pins control the polarity of the
phase/frequency detectors for PLL and PLL, respectively. In
addition, when Mode is high, the R counter is preceded by a
dual–modulus prescaler. Therefore, the R counter is
completely programmable per Figure 16. Also, either a
crystal or TCXO may be used with the device. See the
summary in Table 3.
R 21
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High Level
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Function of Output A
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0
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0
0
fR
Indicator
General–Purpose Output,
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General–Purpose Output,
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0
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Mode Pin = Low Level
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Output C
Pin 16 — General–Purpose Digital Output
This pin is controllable by bit C5 as either low level or high
impedance per Table 4.
The output driver is an open–drain N–channel MOSFET
connected to Gnd. The ESD (electrostatic discharge)
protection circuit for this pin is tied to Gnd and Vpos. Thus,
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Oscillator
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Supports a crystal only
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Supports crystal or
controls polarity of
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Pin is Pol input and
controls polarity of
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accommodated
increments of 0.5
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Programmable in
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pin
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controls whether
voltages above Vpos are clipped at approximately 0.7 V
above Vpos. If unused, Output C should be left open.
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(ON resistance per
Electrical Table)
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Low level
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1
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High impedance
Output B
Pin 25 — General–Purpose Digital Output
This pin is controllable by bits C6 and C1 as either low
level, high level, or high impedance per Table 5. Note that
whenever the main PLL is placed in standby by bit C1, Output
B is forced to high impedance. The three–state MOSFET
output is slew–rate limited. If unused, Output B should be left
open.
Table 5. Output B Programming
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*Power–up default.
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0
Bit C6
State of
Output B Pin
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Condition of
Main PLL
0
0
Low level
Active
1
High impedance*
Standby*
1
0
High level
Active
1
1
High impedance
Standby
fout/Pol and fout/Pol
Pins 28 and 27 — Dual–purpose Outputs/Inputs
These pins are outputs when the Mode pin is low and
inputs when the Mode pin is high.
When the Mode pin is low, these pins are small–signal
differential outputs fout and fout with a frequency derived from
the signal present at the Osce pin. The frequency of the
output signal is per Table 6. If this function is not needed, the
Mode pin should be tied high, which minimizes supply
current. In this case, these inputs must be tied high or low per
Tables 7 and 8.
Table 6. fout and fout Frequency
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