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| 型號(hào)： | MC145230 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器) |
| 中文描述： | 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 28/71頁 |
| 文件大小： | 906K |
| 代理商： | MC145230 |
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MC145225 MC145230
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MOTOROLA RF/IF DEVICE DATA
Figure 20. PDout–Hi and PDout–Lo Detector Output Characteristics
*At this point, when both fR and fV are in phase, the output source and sink circuits are turned on for a short interval.
NOTES:
1. The detector generates error pulses during out–of–lock conditions. When locked in phase and frequency, the output is high impedance and
the voltage at that pin is determined by the low–pass filter capacitor.
2. Waveform shown applies when the fout/Pol pin is low and the Mode pin is high.
3. When the fout/Pol pin is high and Mode is high, the PDout–Hi and PDout–Lo waveform is inverted.
4. The waveform shown is also the default when the Mode pin is low.
fR
Reference
Osce
÷
R)
fV
VCO Feedback
(fin
÷
N)
PDout–Hi,
PDout–Lo
Source Current
Float
Sink Current
*
Figure 21. PDout Detector Output Characteristics
*At this point, when both fR and fV are in phase, the output source and sink circuits are turned on for a short interval.
NOTES:
1. The detector generates error pulses during out–of–lock conditions. When locked in phase and frequency, the output is high impedance
and the voltage at that pin is determined by the low–pass filter capacitor.
2. Waveform shown applies when the fout/Pol pin is low and the Mode pin is high.
3. When the fout/Pol pin is high and Mode is high, the PDout waveform is inverted.
4. The waveform shown is also the default when the Mode pin is low.
fR
Reference
Osce
÷
R )
fV
VCO Feedback
(fin
÷
N )
PDout
High Voltage
High Z
Low Voltage
*
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