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6.5 Notes on Using Watchdog Timer
6.5
Notes on Using Watchdog Timer
This section lists points to note when using the watchdog timer.
s Notes on Using Watchdog Timer
r Stopping watchdog timer
Once activated, the watchdog timer can not stop until a reset generates.
r Count clock selection
The only time the count clock select bit (WDTC: CS) can be changed is at watchdog timer
activation. You can change it by writing the desired state to the count clock select bit (WDTC:
CS) at the same time as you write "0101B" to the watchdog control bits (WDTC: WTE3 to
WTE0) to activate the watchdog timer. Therefore, the CS bit cannot be changed by a bit
operation instruction. Do not change the CS bit after activating the timer.
In the subclock mode, the main clock source oscillation is stopped, which means that the
timebase timer also stops.
For the watchdog timer to operate in subclock mode, then, the watch prescaler must have been
selected in advance as the count clock (WDTC: CS = 1).
r Clearing watchdog timer
Clearing the counter being used as a count clock of the watchdog timer (timebase timer or
watch prescaler) also simultaneously clears the watchdog timer counter.
The watchdog timer counter is cleared on changing to sleep, stop or watch mode.
r Notes on programming
When writing a program in which the watchdog timer is repeatedly cleared in the main loop,
including interrupt processing, is less than the minimum watchdog timer interval time.
r Operation in subclock mode
If the watchdog reset signal is generated in subclock mode, operation will start in main clock
mode after an oscillation stabilization delay time. Therefore, if the device has the reset signal
output option, a reset signal will be output during the oscillation stabilization delay time.