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CHAPTER 4 I/O PORTS
4.5.2
Operation of Port 4, Port 6 and Port 7
This section describes the operations of the port 4, port 6 and port 7.
s Operation of Port 4, 6, and 7
r Operation as an output port
When used as an output-only port (mask option), the pins cannot be used for LCDC common
and segment outputs.
Writing data to the PDR4, 6, and 7 register stores the data in the output latches. When the
output latch value is "0" the output transistor turns "ON" and an "L" level is output from the
pin. When the output latch value is "1", the transistor turns "OFF" and the pin goes to the
high-impedance state. For port 4 and 6 (mask option), if a pull-up is set to the output pin, the
pin goes to the pull-up state when the output latch value is "1".
Reading the PDR4, 6, and 7 register always returns the output latch data.
r Operation as an LCDC common and segment output
When the LCDC output option is selected, set the PDR4, 6, and 7-register bits
corresponding to the LCDC common and segment output pins to "1" to turn the output
transistor "OFF".
You cannot read the LCDC output data by reading PDR4, 6 or 7. (If you read the PDR
registers you will get the output latch data, not the LCDC output data.)
r Operation at reset
Resetting the CPU initializes the PDR4, 6, and 7 register values to "1". This turns "OFF" the
output transistor for all pins and sets the pins to the high-impedance state.
r Operation in stop and watch modes
The output transistors are forcibly turned "OFF" and the pins go to the high-impedance state if
the pin state specification bit in the standby control register (STBC: SPL) is "1" when the device
changes to stop or watch mode.