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11.4 A/D Converter Interrupts
The A/D converter has the following two interrupts:
Conversion completion for the A/D conversion function
Match of the input voltage and the comparison condition
s Interrupt for A/D Conversion Function
When A/D conversion completes, the interrupt request flag bit (ADC1: ADI) is set to "1". At this
time, an interrupt request (IRQB) to the CPU is generated if the interrupt request enable bit is
enabled (ADC2: ADIE = "1"). Write "0" to the ADI bit in the interrupt processing routine to clear
the interrupt request.
The ADI bit is set after completion of A/D conversion, regardless of the ADIE bit value.
Note:
An interrupt request is generated immediately if the ADI bit is "1" when the ADIE bit is
changed from disabled to enabled ("0" --> "1").
s Interrupt for Sense Function
When the specified comparison condition is satisfied after completion of comparison of the input
voltage and compare voltage, the interrupt request flag bit (ADC1: ADI) is set to "1".
At this time, an interrupt request (IRQB) to the CPU is generated if the interrupt request enable
bit is enabled (ADC2: ADIE = "1"). Write "0" to the ADI bit in the interrupt processing routine to
clear the interrupt request.
The ADI bit is set when the comparison condition is satisfied, regardless of the ADIE bit value.
Note:
An interrupt request is generated immediately if the ADI bit is "1" when the ADIE bit is
changed from disabled to enabled ("0" --> "1").
s Register and Vector Table for A/D Converter Interrupt
Reference:
See Section 3.4.2 "Interrupt Processing" for details on the operation of interrupt.
Table 11.4-1 Register and Vector Table for A/D Converter Interrupt
Interrupt
Interrupt level settings register
Vector table address
Register
Setting bits
Upper
Lower
IRQB
ILR3 (007EH)
LB1 (Bit 7)
LB0 (Bit 6)
FFE4H
FFE5H