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4.4 Port 3
4.4.2
Operation of Port 3
This section describes the operations of the port 3.
s Operation of Port 3
r Operation as an output port (P30/PWM1/BZ only)
Writing data to the PDR3 register stores the data in the output latch. The pin outputs the data
stored in the output latch at P30.
Reading the PDR3 register always returns the output latch value.
r Operation as a peripheral output (P30/PWM1/BZ only)
Setting the output enable bit of the peripheral to "enable" makes the corresponding pin a
peripheral output.
You cannot read the peripheral output value by reading PDR3. (PDR3 contains the output
latch value.)
r Operation as an input port (P31/X0A and P32/X1A only)
Writing data to the PDR3 registers stores the data in the output latch but does not output the
data to the pin.
Reading the PDR3 register returns the pin value.
For single clock product, if P31 and P32 are not used as input pins, P31 and P32 should be
connected to pull-up or pull-down resistor.
r Operation at reset
Resetting the CPU initializes the PDR3 register values to "1". This outputs "H" level at P30.
P31 and P32 are input pins.
Pin state of P30 is undetermined until the internal clock starts operation.
r Operation in stop and watch modes
The output transistors are forcibly turned "OFF" and the pins go to the high-impedance state
if the pin state specification bit in the standby control register (STBC:SPL) is "1" when the
device changes to stop or watch mode.
To avoid current leakage, it is recommended to remain a known logic level of the input port
pins during the standby mode.
Table 4.4-4 "Port-3 Pin State" lists the port-3 pin states.