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8.1 Overview of 8/16 -bit Timer/Counter
tinst: Instruction cycle (affected by clock mode, etc.)
text: External clock period
Note:
Calculation example for the interval time and square wave frequency:
In this example, the main clock source oscillation (FCH) is 4.2 MHz, the timer 1 data register
(T1DR) value is set to "DDH(221)" and the count clock cycle is set to the 8-bit mode
operation at 2 tinst. In this case, the timer 1 interval time and frequency of square wave
output from the TO pin (where the PWM timer operates continuously and the value of the
T1DR register is constant) are calculated as follows.
Assume that the main clock mode (SCS = 1) and the highest clock speed (CS1/CS0 = 11B)
has been selected via the system clock control register (SYCC: SCS = 1, CS1 = 11B, CS0 =
11B) (1 instruction cycle = 4/FCH).
Table 8.1-2 Timer 2 Interval Times and Square Wave Frequencies In 8-bit Mode
Count clock cycle
Interval time
Square wave output range (Hz)
Internal count clock
2 tinst
2 tinst to 2
9 t
inst
1/(22 tinst) to 1/(2
10 t
inst)
32 tinst
25 tinst to 2
13 t
inst
1/(26 tinst) to 1/(2
14 t
inst)
512 tinst
29 tinst to 2
17 t
inst
1/(210 tinst) to 1/(2
18 t
inst)
External clock
1 text
1 text to 2
8 t
ext
1/(2 text) to 1/(2
9 t
ext)
Table 8.1-3 Interval Times and Square Wave Frequencies 16-bit Mode
Count clock cycle
Interval time
Square wave output range (Hz)
Internal count clock
2 tinst
2 tinst to 2
17 t
inst
1/(22 tinst) to 1/(2
18 t
inst)
32 tinst
25 tinst to 2
21 t
inst
1/(26 tinst) to 1/(2
22 t
inst)
512 tinst
29 tinst to 2
25 t
inst
1/(210 tinst) to 1/(2
26 t
inst)
External clock
1 text
1 text to 2
16 t
ext
1/(2 text) to 1/(2
17 t
ext)
Interval time
= (2
4/FCH)
(T1DR register value + 1)
= (8/4.2 MHz)
(221 + 1)
422.9 s
Output frequency
= FCH/(2
8
(T1DR register value + 1))
= 4.2 MHz/ (16
(221 + 1))
1.18 kHz