MOTOROLA
M68060 USER’S MANUAL
ix
TABLE OF CONTENTS
Section 1
Introduction
1.1
1.1.1
1.1.2
1.1.2.1
1.1.2.2
1.2
1.3
1.4
1.4.1
1.4.2
1.4.2.1
1.4.2.2
1.4.2.3
1.4.2.4
1.4.2.5
1.4.2.6
1.4.2.6.1
1.4.2.6.2
1.4.3
1.5
1.6
1.7
1.8
1.9
1.10
Differences Among M68060 Family Members..............................................1-3
MC68LC060................................................................................................1-3
MC68EC060 ...............................................................................................1-3
Address Translation Differences ..............................................................1-3
Instruction Differences..............................................................................1-3
Features........................................................................................................1-4
Architecture...................................................................................................1-4
Processor Overview......................................................................................1-5
Functional Blocks........................................................................................1-5
Integer Unit .................................................................................................1-7
Instruction Fetch Unit................................................................................1-7
Integer Unit...............................................................................................1-8
Floating-Point Unit....................................................................................1-8
Memory Units ...........................................................................................1-9
Address Translation Caches ....................................................................1-9
Instruction and Data Caches ....................................................................1-9
Cache Organization..............................................................................1-10
Cache Coherency.................................................................................1-10
Bus Controller...........................................................................................1-10
Processing States.......................................................................................1-10
Programming Model....................................................................................1-11
Data Format Summary................................................................................1-14
Addressing Capabilities Summary..............................................................1-14
Instruction Set Overview.............................................................................1-15
Notational Conventions...............................................................................1-21
Section 2
Signal Description
2.1
2.1.1
2.1.2
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
Address and Control Signals ........................................................................2-3
Address Bus (A31–A0) ...............................................................................2-3
Cycle Long-Word Address (CLA) ...............................................................2-4
Data Bus (D31–D0).......................................................................................2-4
Transfer Attribute Signals .............................................................................2-4
Transfer Cycle Type (TT1, TT0) .................................................................2-4
Transfer Cycle Modifier (TM2–TM0)...........................................................2-4
Transfer Line Number (TLN1, TLN0)..........................................................2-5
User-Programmable Page Attributes (UPA1, UPA0)..................................2-5
Read/Write (R/W) .......................................................................................2-6