Introduction
1-16
M68060 USER’S MANUAL
MOTOROLA
Table 1-3. Instruction Set Summary
Opcode
Operation
Syntax
ABCD
BCD Source + BCD Destination + X
Destination
ABCD Dy,Dx
ABCD –(Ay),–(Ax)
ADD <ea>,Dn
ADD Dn,<ea>
ADDA <ea>,An
ADDI #<data>,<ea>
ADDQ #<data>,<ea>
ADDX Dy,Dx
ADDX –(Ay),–(Ax)
AND <ea>,Dn
AND Dn,<ea>
ANDI #<data>,<ea>
ANDI #<data>,CCR
ADD
Source + Destination
Destination
ADDA
ADDI
ADDQ
Source + Destination
Immediate Data + Destination
Immediate Data + Destination
Destination
Destination
Destination
ADDX
Source + Destination + X
Destination
AND
Source
Λ
Destination
Destination
ANDI
Immediate Data
Λ
If supervisor state
Λ
CCR
Destination
Destination
ANDI to CCR Source
CCR
ANDI to SR
then Source
Λ
SR
SR
else TRAP
ANDI #<data>,SR
ASL, ASR
Destination Shifted by count
Destination
ASd Dx,Dy
ASd #<data>,Dy
ASd <ea>
1
Bcc
If condition true
then PC + dn
PC
Bcc <label>
BCHG
~(bit number of Destination)
~(bit number of Destination)
~(bit number of Destination)
0
bit number of Destination
~(bit field of Destination)
0
bit field of Destination
bit field of Source
Dn
bit offset of Source
Dn
bit offset of Source Bit Scan
Dn
Dn
bit field of Destination
1s
bit field of Destination
bit field of Destination
Run breakpoint acknowledge cycle;
TRAP as illegal instruction
PC + dn
PC
~(bit number of Destination)
Z;
1
bit number of Destination
SP – 4
SP; PC
(SP); PC + dn
PC
Z;
(bit number) of Destination
Z;
BCHG Dn,<ea>
BCHG #<data>,<ea>
BCLR Dn,<ea>
BCLR #<data>,<ea>
BFCHG <ea>{offset:width}
BFCLR <ea>{offset:width}
BFEXTS <ea>{offset:width},Dn
BFEXTU <ea>{offset:width},Dn
BFFFO <ea>{offset:width},Dn
BFINS Dn,<ea>{offset:width}
BFSET <ea>{offset:width}
BFTST <ea>{offset:width}
BCLR
BFCHG
BFCLR
BFEXTS
BFEXTU
BFFFO
BFINS
BFSET
BFTST
bit field of Destination
BKPT
BKPT #<data>
BRA
BRA <label>
BSET Dn,<ea>
BSET #<data>,<ea>
BSR <label>
BTST Dn,<ea>
BTST #<data>,<ea>
CAS Dc,Du,<ea>
BSET
BSR
BTST
–(bit number of Destination)
Z;
CAS
8
CAS Destination – Compare Operand
cc;
if Z, Update Operand
Destination
else Destination
Compare Operand
CAS2 Destination 1 – Compare 1
cc;
if Z, Destination 2 – Compare
cc;
if Z, Update 1
Destination 1;
Update 2
Destination 2
else Destination 1
Compare 1;
Destination 2
Compare 2
If Dn < 0 or Dn > Source
then TRAP
If Rn < LB or If Rn > UB
then TRAP
If supervisor state
then invalidate selected cache lines
else TRAP
CAS2
2
CAS2 Dc1–Dc2,Du1–Du2,(Rn1)–
(Rn2)
CHK
CHK <ea>,Dn
CHK2
2
CHK2 <ea>,Rn
CINV
CINVL <caches>, (An)
CINVP <caches>, (An)
CINVA <caches>