Bus Operation
7-62
M68060 USER’S MANUAL
MOTOROLA
Table 7-8. MC68060-Arbitration Protocol State Transition Conditions
Present
State
Condition RSTI BG
TS sampled
as an input
(TSI))
—
—
—
—
—
—
—
N
—
—
A
A
A
N
N
N
A
A
N
N
N
N
N
—
—
A
—
—
SNOOP
BTT sampled
as an input
(BTTI)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
N
A
A
A
—
—
—
—
—
—
Internal
Bus Request
(IBR)
—
—
—
—
—
—
—
—
N
A
—
—
—
—
N
A
—
—
—
N
A
—
—
N
A
—
—
—
Transfer
in
Progress
—
—
—
N
A
A
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
End of
Reset
A1
A2
A3
B1
B2
B3
B4
C1
C2
C3
C4
D1
D2
D3
D4
D5
E1
E2
E3
E4
E5
E6
F1
F2
F3
F4
G1
—
A
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
A
—
A
N
N
N
N
A
N
A
A
N
—
—
N
A
A
—
—
—
A
A
N
N
A
A
N
—
—
—
—
—
—
—
—
—
—
—
—
—
A
N
—
—
—
A
N
—
—
—
—
—
—
—
—
—
—
—
—
—
—
N
A
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Reset
Implicit Own
AM Implicit
End Tenure
Explicit Own
End Tenure
Explicit Own
AM Implicit
Implicit Own
Explicit Own
Violation
Snoop
AM Explicit
AM Implicit
Implicit Own
Explicit Own
Snoop
AM Explicit
AM Explicit
Implicit Own
Explicit Own
AM Implicit
AM Implicit
Implicit Own
Explicit Own
Violation
AM Explicit
Reset
Explicit
Own
End
Tenure
AM
Implicit
AM
Explicit
Implicit
Own
Snoop
Any
NOTES:
1) “N” means negated; “A” means asserted.
2) End of cycle: Whatever terminates a bus transaction whether it is normal, bus error, or retried. Note that long-word
bus cycles that result from a burst inhibited line transfer are considered part of that original line transfer.
3) Conditions C4 and F4 indicate that an alternate master has taken bus ownership without waiting for the current master
to assert BTT.
4) IBR refers to an internal bus request. The output signal BR is a registered version of IBR.
5) BTTI refers to BTT when sampled as an input.
6) SNOOP denotes the condition in which SNOOP is sampled asserted, and TT1 = 0.
7) In this state diagram, BGR is assumed always asserted; hence, bus cycles within a locked sequence are treated no
differently from nonlocked bus cycles, except that the processor takes an extra BCLK period in the end tenure state
to allow for LOCK and LOCKE to negate. If BGR is negated and a locked sequence is in progress, the processor does
not relinquish the bus if BG is negated until the end of the last bus cycle in the locked sequence.
8) The processor does not require a valid acknowledge termination for snooped accesses. The only restriction is that a
snoop cycle be performed at no more than a maximum rate of once every two BCLK cycles. This state diagram prop-
erly emulates this behavior.