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| 型號(hào)： | M68060 |
| 廠商： | Motorola, Inc. |
| 英文描述： | M68060 User Manual |
| 中文描述： | M68060用戶手冊(cè) |
| 文件頁(yè)數(shù)： | 152/416頁(yè) |
| 文件大?。?/td> | 1451K |
| 代理商： | M68060 |
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Floating-Point Unit
6-34
M68060 USER’S MANUAL
MOTOROLA
The INEX2 exception is the condition that exists when any operation, except the input of a
packed decimal number, creates a floating-point intermediate result whose infinitely precise
mantissa has too many significant bits to be represented exactly in the selected rounding
precision or in the destination data format. If this condition occurs, the INEX2 bit is set in the
FPSR EXC byte, and the infinitely precise result is rounded. Table 6-16 lists these rounding
mode values.
The INEX1 and INEX2 exceptions are always maskable. Therefore, any INEX exception
goes directly to the user INEX exception handler. When an INEX2 or INEX1 bit in the FPSR
EXC byte is set, the rounded result (listed in Table 6-16), is written to the destination. The
FPCR MODE bits determine the rounding mode. The PREC bits in the FPCR determine the
rounding precision if the destination is a floating-point data register; otherwise, if the desti-
nation is memory or an integer data register, the destination format determines the rounding
precision. If one of the instructions has a forced precision, the instruction determines the
rounding precision. If the INEX2 or INEX1 condition exists and if the corresponding INEX bit
in the FPCR exception enable byte is set, then the user INEX exception handler is taken.
6.6.7.1 TRAP DISABLED RESULTS (FPCR INEX1 BIT AND INEX2 BIT CLEARED.
The
result is rounded and then written to the destination.
6.6.7.2 TRAP ENABLED RESULTS (EITHER FPCR INEX1 BIT OR INEX2 BIT SET).
The result is rounded and then written to the destination as in the trap disabled case. For an
FMOVE OUT instruction, control is passed to the user INEX handler as a post-instruction
exception. Otherwise, for other floating-point instructions that have floating-point data regis-
ter destinations, control is passed to the user INEX handler as a pre-instruction exception
when the next floating-point instruction is encountered.
The user INEX exception handler must execute an FSAVE as its first floating-point instruc-
tion. At this point, the destination contains the rounding mode values as listed in Table 6-16,
and the user INEX exception handler can choose to modify these values. If the inexact con-
version is the only exception that occurs during the execution of an instruction, the value of
the exception operand is invalid. If multiple exceptions occur during an instruction, the
exception operand value is related to a higher priority exception. The FPIAR points to the
instruction that caused the exception. If the instruction is an FMOVE OUT, the integer stack
frame format $3 contains the effective address of the destination memory operand. If the
destination is an integer data register, the effective address field is undefined.
Table 6-16. Rounding Mode Values
Rounding Mode
Result
RN
The representable value nearest to the infinitely precise intermediate value is the
result. If the two nearest representable values are equally near (a tie), then the one
with the least significant bit equal to zero (even) is the result. This is sometimes
referred to as “round to nearest, even.”
The result is the value closest to and no greater in magnitude than the infinitely
precise intermediate result. This is sometimes referred to as the “chop mode,”
since the effect is to clear the bits to the right of the rounding point.
The result is the value closest to and no greater than the infinitely precise interme-
diate result (possibly minus infinity).
The result is the value closest to and no less than the infinitely precise intermedi-
ate result (possibly plus infinity).
RZ
RM
RP
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