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| 型號(hào)： | M68060 |
| 廠商： | Motorola, Inc. |
| 英文描述： | M68060 User Manual |
| 中文描述： | M68060用戶手冊(cè) |
| 文件頁(yè)數(shù)： | 180/416頁(yè) |
| 文件大?。?/td> | 1451K |
| 代理商： | M68060 |
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Bus Operation
MOTOROLA
M68060 USER’S MANUAL
7-25
processor negates TIP during the next clock. The processor also three-states the data bus
during the next clock following termination of the write transfer.
7.7.4 Line Write Cycles
The processor uses line write bus cycles to access a 16-byte operand for a MOVE16 instruc-
tion and to support cache line pushes. Both burst and burst-inhibited transfers are sup-
ported. Figure 7-20 and Figure 7-22 illustrate a flowchart and functional timing diagram for
a line write bus cycle.
Clock 1 (C1)
The line write cycle starts in C1. During C1, the processor places valid values on the ad-
dress bus and transfer attributes. The processor asserts TS during C1 to indicate the be-
ginning of a bus cycle. If not already asserted from a previous bus cycle, the TIP signal is
also asserted at this time to indicate that a bus cycle is active.
The processor pre-conditions the data bus during C1 to improve AC timing. The process
of pre-conditioning involves reinforcing the logic level that is already at the data pin. If the
voltage level is originally zero volts, nothing is done; if the voltage level is 3.3 V, that volt-
age level is reinforced; however, if the voltage level is originally 5 V, the processor drives
that data pin from 5 V down to 3.3 V. Note that no active logic change is done at this time.
The actual logic level change is done in C2. This pre-conditioning affects operation prima-
rily when using the processor in a 5-V system.
For user and supervisor mode accesses that are translated by the corresponding memory
unit, UPAx signals are driven with the values from the matching U1 and U0 bits. The TTx
and TMx signals identify the specific access type. The R/W signal is driven low for a write
cycle, and the SIZx signals indicate line size. Refer to
Section 4 Memory Management
Unit
for information on the MC68060 and MC68LC060 memory units and
Appendix B
MC68EC060
for information on the MC68EC060 memory unit.
Clock 2 (C2)
During C2, the processor negates TS and drives the data bus with the data to be written.
The selected device uses R/W, SIZ1, SIZ0, or BSx to register the data on the data bus.
Concurrently, the selected device asserts TA and either negates TBI to indicate it can or
asserts TBI to indicate it cannot support a burst transfer.
The MC68060 implements a special mode called the acknowledge termination ignore
state capability to aid in high-frequency designs. In this mode, the processor begins sam-
pling termination signals such as TA after a user-programmed number of BCLK rising
edges has expired. The SAS signal is provided as a status output to indicate which BCLK
rising edge the processor begins to sample the termination signals. If this mode is dis-
abled, SAS is asserted during C2 to indicate that the processor immediately begins sam-
pling the terminations signals. Refer to
7.14.1 Acknowledge Termination Ignore State
Capability
for details on this special mode.
Assuming that the acknowledge termination ignore state capability is disabled, the pro-
cessor samples the level of TA and TBI at end of C2. If TA is asserted, the transfer termi-
nates. If TA is not recognized asserted, the processor inserts wait states instead of
terminating the transfer. The processor continues to sample TA and TBI on successive
rising edges of BCLK until TA is recognized asserted. If TBI was negated with the asser-
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