Signal Description
2-2
M68060 USER’S MANUAL
MOTOROLA
Transfer Retry Acknowl-
edge
Transfer Error Acknowl-
edge
Transfer Cycle Burst In-
hibit
Transfer Cache Inhibit
Snoop Control
Bus Request
Bus Grant
Bus Grant Relinquish
Control
TRA
Indicates the need to rerun the bus cycle.
TEA
Indicates an error condition exists for a bus transfer.
TBI
Indicates the slave cannot handle a line burst access.
TCI
Indicates the current bus transfer should not be cached.
Indicates the MC68060 should snoop bus activity while it is not the bus master.
Asserted by the processor to request bus mastership.
Asserted by an arbiter to grant bus mastership privileges to the processor.
Qualifies BG by indicating the degree of necessity for relinquishing bus owner-
ship when BG is negated.
Indicates the MC68060 has relinquished the bus in response to the external ar-
biter’s negation of BG.
Asserted by the current bus master to indicate it has assumed ownership of the
bus.
Dynamically disables the internal caches to assist emulator support.
Disables the translation mechanism of the MMUs.
Processor reset.
Asserted during execution of a RESET instruction to reset external devices.
Provides an encoded interrupt level to the processor.
Indicates an interrupt is pending.
Used during an interrupt acknowledge transfer to request internal generation of
the vector number.
PST4–PST0 Indicates internal processor status.
CLK
Clock input used for all internal logic timing.
Defines the speed of the system bus clock to be full, 1/2, or 1/4 the speed of the
processor clock.
Selects between IEEE 1149.1 compliance operation and emulation mode oper-
ation.
TCK
Clock signal for the IEEE P1149.1 test access port (TAP).
TMS
Selects the principal operations of the test-support circuitry.
TDI
Serial data input for the TAP.
TDO
Serial data output for the TAP.
TRST
Provides an asynchronous reset of the TAP controller.
THERM1,
THERM0
VCC
Power supply.
GND
Ground connection.
SNOOP
BR
BG
BGR
Bus Tenure Termination
BTT
Bus Busy
BB
Cache Disable
MMU Disable
Reset In
Reset Out
Interrupt Priority Level
Interrupt Pending
CDIS
MDIS
RSTI
RSTO
IPL2–IPL0
IPEND
Autovector
AVEC
Processor Status
Processor Clock
Clock Enable
CLKEN
JTAG Enable
JTAG
Test Clock
Test Mode Select
Test Data Input
Test Data Output
Test Reset
Thermal Resistor Con-
nections
Power Supply
Ground
Provides thermal sensing information.
Table 2-1. Signal Index (Continued)
Signal Name
Mnemonic
Function