參數(shù)資料
型號(hào): M66271FP
元件分類: 顯示控制器
英文描述: 320 X 240 DOTS DOT MAT LCD DSPL CTLR, PQFP80
封裝: QFP-80
文件頁(yè)數(shù): 6/30頁(yè)
文件大?。?/td> 309K
代理商: M66271FP
M66271FP
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 12 of 27
Description of Cycle Steal
Basic Timing
Basic timing of M66271FP is two clocks of OSC (internal clock after dividing OSC1 input).
Assign first clock to accessing from MPU to VRAM and second clock to transferring of display data from VRAM to
LCD.
OSC
(Internal clock after
dividing OSC1 input)
CP output
(Display data transfer)
Access
from MPU
to VRAM
Data transfer
from VRAM
to LCD
MPU
LCD
Basic cycle
Figure 2 Basic Timing
Operation Cycle of MPU Access (During
WAIT Output)
Writing or reading operation for VRAM during cycle steal needs 1 cycle in best case or 3 cycles in worst case,
according to the condition of the internal cycle steal at staring access requested from MPU.
Best case
Worst case
Cycle of
LCD access
Cycle of
MPU access
Cycle of
LCD access
Cycle of
MPU access
Cycle of
LCD access
MCS
WAIT
MCS
WAIT
Ex.) Assuming that
MCS input is later than RD, LWR and HWR input.
Cancel WAIT, when synchronize
with rising edge of MPUCLK
MPUCLK
Cancel WAIT, when synchronize
with rising edge of MPUCLK
Figure 3 Operation Cycle of MPU Access
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