參數(shù)資料
型號(hào)： M66271FP
元件分類(lèi)： 顯示控制器
英文描述： 320 X 240 DOTS DOT MAT LCD DSPL CTLR, PQFP80
封裝： QFP-80
文件頁(yè)數(shù)： 20/30頁(yè)
文件大?。?/td> 309K
代理商： M66271FP
M66271FP
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 25 of 27
(5) Write to VRAM (
RD = "H")
MCS
LWR
(+
HWR)
WAIT
D <7:0>
(D <15:0>)
A <13:0>
(+
BHE)
Address is established
th (WR-A)
tpHL (WR-WAIT)
th (MCS-A)
th (MCS-D)
tsu (D-MCS)
tsu (A-MCS)
tsu (A-WR)
MPUCLK
tC (CLK)
tw (MCS)
tw (WR)
tpLH (CLK-WAIT)
Term of cycle steal access
tWH (CLK)
tWL (CLK)
tpHL (MCS-WAIT)
tsu (D-WR)
th (WR-D)
Data input is established
(6) Read from VRAM (
LWR, HWR = "H")
MCS
RD
WAIT
D <7:0>
(D <15:0>)
A <13:0>
Address is established
th (RD-A)
tpd (D-WAIT)
th (MCS-A)
tpHL (RD-WAIT)
tdis (MCS-D)
tsu (A-MCS)
ta (MCS-D)
ta (RD-D)
tsu (A-RD)
MPUCLK
tC (CLK)
tpLH (CLK-WAIT)
Term of cycle steal access
tWH (CLK)
tWL (CLK)
tpHL (MCS-WAIT)
tdis (RD-D)
Data output is established
Notes: 3. Reading/writing operation for VRAM during cycle steal needs 1 tc (Internal) in best case or 3 tc (Internal) in
worst case, according to the condition of the internal cycle steal at starting access requested from MPU.
tc (Internal) = Clock cycle time after setting division of OSC1.
Data output D in reading is established before changing
WAIT to "H".
4. Limits of
MCS, LWR (+HWR) and RD are prescribed by the input signal of last change to "L" in starting
access, and by the input signal of first change to "H" in ending access.
5. Always once return
MCS, LWR (+HWR) or RD to "H" after canceling WAIT output.
In case of latching "L", as don't output next
WAIT, this is cause of error action.
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