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參數(shù)資料
| 型號(hào)： | M66271FP |
| 元件分類： | 顯示控制器 |
| 英文描述： | 320 X 240 DOTS DOT MAT LCD DSPL CTLR, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 29/30頁 |
| 文件大?。?/td> | 309K |
| 代理商： | M66271FP |
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M66271FP
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 6 of 27
Switching Characteristics
(VDD = 5 V ± 10%, Ta = 0 to +70°C, CL = 50 pF)
Item
Symbol
Min
Typ
Max
Unit
IOCS data access time
MCS data access time
RD data access time
ta (IOCS-D)
ta (MCS-D)
ta (RD-D)
—
70
ns
Output disable time after IOCS
Output disable time after MCS
Output disable time after RD
tdis (IOCS-D)
tdis (MCS-D)
tdis (RD-D)
—
20
ns
WAIT output propagation time after MCS
WAIT output propagation time after WR
WAIT output propagation time after RD
tpHL (MCS-WAIT)
tpHL (WR-WAIT)
tpHL (RD-WAIT)
—
40
ns
WAIT output propagation time after MPUCLK
tpLH (CLK-WAIT)
—
20
ns
CP output propagation time after OSC
tpd (OSC-CP)
—
40
ns
LP output propagation time after OSC
tpLH (OSC-LP)
tpHL (OSC-LP)
—
40
ns
UD access time
ta (UD)
—
40
ns
FLM output propagation time after OSC
tpLH (OSC-FLM)
tpHL (OSC-FLM)
—
40
ns
M output propagation time after OSC
tpd (OSC-M)
—
40
ns
LCDENB output propagation time after OSC
tpLH (OSC-LE)
tpHL (OSC-LE)
—
40
ns
Data definite time before canceling WAIT
tpd (D-WAIT)
0
—
ns
Timing Requirements
(VDD = 5 V ± 10%, Ta = 0 to +70°C)
(1) Accessing to Control Register
Item
Symbol
Min
Typ
Max
Unit
IOCS pulse width
LWR pulse width
tW (IOCS)
tW (LWR)
70
—
ns
Data set up time before falling edge of IOCS
Data set up time before falling edge of LWR
tsu (D-IOCS)
tsu (D-LWR)
0
—
ns
Data hold time after rising edge of IOCS
Date hold time after rising edge of LWR
th (IOCS-D)
th (LWR-D)
15
—
ns
Address set up time before falling edge of IOCS
Address set up time before falling edge of LWR
Address set up time before falling edge of RD
tsu (A-IOCS)
tsu (A-LWR)
tsu (A-RD)
15
—
ns
Address hold time after rising edge of IOCS
Address hold time after rising edge of LWR
Address hold time after rising edge of RD
th (IOCS-A)
th (LWR-A)
th (RD-A)
15
—
ns
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