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| 型號： | M66271FP |
| 元件分類： | 顯示控制器 |
| 英文描述： | 320 X 240 DOTS DOT MAT LCD DSPL CTLR, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 4/30頁 |
| 文件大小： | 309K |
| 代理商： | M66271FP |
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M66271FP
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 10 of 27
Combination of Control Input Pins for MPU Interface
Table 1 to 6 show conditions of input setting when access the control register and VRAM from MPU.
(1) Access control register (Use address = A <4:0>, Data = D <7:0>)
Table 1
IOCS
LWR
RD
Operation
L
H
Write to control register
L
H
L
Read from control register
H
X
Invalid
(2) Writing to VRAM
(2-1) When use 8-bit MPU (MPUSEL = "L",
BHE = HWR = "H": set)
Table 2
MPU
SEL
MCS
BHE
A <0>
HWR
LWR
Odd
Address
Even
Address
Valid Data Bus
Width of MPU
L
Invalid
Write
H
L
Write
Invalid
8-bit
L
X
H
L
H
X
H
X
Invalid
(2-2) When use 16-bit MPU (In MPU controls byte access with A <0> and
BHE, MPUSEL = HWR = "H": set)
Table 3
MPU
SEL
MCS
BHE
A <0>
HWR
LWR
Upper
Byte
Lower
Byte
Valid Data Bus
Width of MPU
L
Write
16-bit
L
H
Invalid
L
Write
Invalid
Upper 8-bit
L
H
Invalid
L
Invalid
Write
Lower 8-bit
L
H
Invalid
L
Invalid
Write
Lower 8-bit
L
H
X
H
X
Invalid
← Even if
A <0> = "H",
enable to write
(2-3) When use 16-bit MPU
(In MPU controls byte access with
LWR and HWR, MPUSEL = BHE = A <0> = "H": set)
Table 4
MPU
SEL
MCS
BHE
A <0>
HWR
LWR
Upper
Byte
Lower
Byte
Valid Data Bus
Width of MPU
L
Write
16-bit
L
H
Write
Invalid
Upper 8-bit
L
Invalid
Write
Lower 8-bit
L
H
X
Invalid
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