參數(shù)資料
型號(hào)： M66271FP
元件分類(lèi)： 顯示控制器
英文描述： 320 X 240 DOTS DOT MAT LCD DSPL CTLR, PQFP80
封裝： QFP-80
文件頁(yè)數(shù)： 27/30頁(yè)
文件大?。?/td> 309K
代理商： M66271FP
M66271FP
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 4 of 27
Pin Description
Item
Pin Name
Input/
Output
Function
Number
of Pins
D <15:0>
Input/
Output
MPU data bus
Connect to MPU data bus.
Selecting 8-bit MPU by MPUSEL input, D <15:8> connect to VDD or VSS
16
A <13:0>
Input
MPU address bus
Connect to MPU address bus. When selecting 8-bit MPU, use A <13:0>. And
selecting16-bit MPU, use A <13:1> for the address bus with combining A <0> and
BHE by the method of access to internal VRAM (Refer to figure 1). Use A <4:0> for
selecting address of control register.
14
IOCS
Input
Chip select input of control register
When this pin is "L", select the internal control register. Assign to I/O space of MPU.
1
MCS
Input
Chip select input of VRAM
When this pin is "L", select the internal VRAM. Assign to memory space of MPU.
1
HWR
Input
High-write strobe input
When this pin is "L", data write to the internal VRAM.
HWR is valid only in using 16-
bit MPU controlled byte access by
LWR and HWR. (Refer to figure 1)
1
LWR
Input
Low-write strobe input
When this pin is ''L", data write to the internal control register or VRAM. (Refer to
figure 1)
1
RD
Input
Read strobe input
When this pin is "L", data read from the internal control register or VRAM. (Refer to
figure 1)
1
MPUSEL
Input
8/16-bit MPU select input
According to MPU, set "VSS" for 8-bit MPU and set "VDD" for 16-bit MPU
1
RESET
Input
Reset input
Use reset signal of MPU. When this pin is "L", initialize all internal control register
and counter.
1
MPUCLK
Input
MPU clock
Input of MPU clock.
1
BHE
Input
Bus-high-enable input
This pin is valid when using 16-bit MPU controlled byte access by A <0> and
BHE
(Refer to figure 1). Connect to "VDD" when using 8-bit MPU.
Set to ''L'' when using the additional function for the LCD module built-in system.
1
MPU
interface
WAIT
Output
WAIT output for MPU
This signal makes WAIT for MPU.
Change
WAIT ''L'' at timing of falling edge of overlapping with MCS and (RD or LWR
or
HWR).
And return to "H" at synchronizing with the rising edge of MPUCLK after internal
processing.
(Output
WAIT only when requested access from MPU to VRAM during cycle steal
access.)
1
UD <3:0>
Output
Display data bus for LCD
Transfer the LCD display data with 4-bit parallel signal.
Mutually output upper/lower data every CP output.
4
CP
Output
Display data transfer clock
Shift clock for the transfer of display data to LCD.
Take the display data of UD <3:0> to LCD at falling edge of CP.
1
LP
Output
Display data latch pulse
This clock use both as the latch pulse of display data for LCD and the transfer of
scanning signal.
LP output when finish the transfer of display data of a line.
Latch of display data and the transfer of scanning signal at falling edge of LP.
1
FLM
Output
First line marker signal
Output the start pulse of scanning line.
This signal is "H" active, the IC for driving scanning line catch FLM at falling edge of
LP.
1
M
Output
LCD alternating signal output
Signal for driving LCD by alternating current.
1
LCD
interface
LCDENB
Output
LCD (ON/OFF) control signal output
Output data which is set at bit "0" of mode register (R1) in control register. This
signal can use for controlling the LCD power supply, because LCDENB set to "L" by
RESET.
1
OSC1
Input
Input pin for oscillator
1
Oscillator
OSC2
Output
Output pin for oscillator
Generate an internal clock.
For crystal oscillator or external clock signal.
1
VDD
—
Power supply (source + 5 V)
7
VSS
—
Ground
12
Others
N.C
—
No connection
10
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