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參數(shù)資料
| 型號： | M66271FP |
| 元件分類： | 顯示控制器 |
| 英文描述： | 320 X 240 DOTS DOT MAT LCD DSPL CTLR, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 2/30頁 |
| 文件大?。?/td> | 309K |
| 代理商： | M66271FP |
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M66271FP
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 8 of 27
Outline
M66271FP is graphic display only controller for displaying a dot matrix type LCD. This IC has a built-in display data
memory (VRAM) which is equivalent to 320
× 240 dots LCD.
Control register
When access the control register from MPU side, use
IOCS, LWR, RD, A <4:0> and D <7:0>. Refer to table 1,
when set control type inputs.
Control registers are R1 to R8 for the normal mode function and R9 to R11 for the exclusive register for the LCD
module built-in system.
VRAM
When access VRAM from MPU side, use
MCS, HWR, LWR, RD, BHE, A <13:0> and D <15:0>. And enable to
correspond to both 8-bit and 16-bit MPU by using MPUSEL input. Refer to figure 1 and table 2 to 6 for a form of
VRAM and input setting for 8/16-bit MPU.
Cycle steal system
Cycle steal is interact method of transferring display data for LCD from VRAM and accessing VRAM from MPU
on the basic cycle of OSC.
Basic timing is two clocks of OSC, and assign first clock to the access from MPU to VRAM and second clock to the
transfer of display data from VRAM to LCD.
In accessing VRAM from MPU, output
WAIT. Change WAIT to "L" at the timing of the falling edge of
overlapping with
MCS and (RD or LWR/HWR). And return to "H" at synchronizing with rising edge of MPUCLK
after internal processing.
Cycle steal system can transfer data with more efficient. This function access with the cycle steal method as taking
WAIT for MPU during the display term with necessity for the display data transfer from built-in VRAM to LCD.
On other side, don't output
WAIT for keeping throughput of MPU during horizontal synchronous term with no
necessity for the display data transfer from VRAM to LCD side.
Refer to the following description of cycle steal.
Output to LCD side
LCD display data UD <3:0> output synchronized with the rising edge of CP output per 4 bits.
LP output synchronized with the falling edge of OSC when finish the transfer of display data for a line.
Enable to adjust the fittest value of the frame frequency requested by the LCD PANEL side with adjusting pulse
width by LPW register.
FLM output, when finish the transfer of display data of 1st line.
M output is the LCD alternating signal which is signal for driving LCD by alternating current.
M-cycle enable to set variably by M-cycle variable register in line unit, and enable to utilize for preventing LCD
from being inferior.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M66272 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:LCD CONTROLLER with VRAM |
| M66272FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:LCD CONTROLLER with VRAM |
| M66273FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:LCD CONTROLLER with VRAM |
| M66280FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:5120 x 8-BIT LINE MEMORY |
| M66280FP(#TB0T) | 制造商:Renesas Electronics Corporation 功能描述: |
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