參數(shù)資料
型號： M58WR064EBZB
廠商： 意法半導(dǎo)體
英文描述： 64 Mbit 4Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory
中文描述： 64兆位4Mb的× 16，多銀行，突發(fā)1.8V電源快閃記憶體
文件頁數(shù)： 80/82頁
文件大?。?/td> 1100K
代理商： M58WR064EBZB
81/82
REVISION HISTORY
Table 44. Document Revision History
Date
Version
Revision Details
08-Apr-2002
-01
First Issue
20-Jun-2002
-02
Part number modified, Synchronous Burst Frequency modified, description of the
Automatic Standby mode added.
Hexadecimal Code for Quadruple Word Program Setup modified.
Double/Quadruple Word Program command descriptions modified.
Description of the Verify Phase in the Enhanced Factory Program command and the
Exit Phase in the Quadruple Enhanced Factory Program command modified.
Parameters in Tables 6, 7, 8, 18, 20, 21, 22, 23, 24, 33, 39, 40, 41 and 43 modified
and/or specified. Figures 4, 7, 12, 13, 15, 16, 17 and 23 modified. Figure 14 added.
21-Oct-2002
2.1
Revision numbering modified: a minor revision will be indicated by incrementing the
digit after the dot, and a major revision, by incrementing the digit before the dot
(revision version 02 equals 2.0).
Revision history moved to end of document.
Bank numbering modified; Figures 21, 22, 23, 24, 27, 28 and 29 modified. 1st Cycle
Addresses modified in Table 5 and note to Figure 13, modified.
Notes added to Figures 12, 21, 22, 23, 24, 27, and 28 and Table 14.
85ns Speed Class removed, 80ns Speed Class added.
70ns Speed Class characterized (certain timings modified).
19-Feb-2003
3.0
Document promoted from Product Preview to full Datasheet status.
Automatic Standby mode explained under Asynchronous Read Mode. Minor text
Bank Erase Command moved from the Standard to the Factory Program
Commands. Number of Bank Erase cycles limited to 100. Erase replaced by Block
Erase in Tables 11 and 12, Dual Operations Allowed in Other Banks and the Same
Bank, respectively.
Overbar removed from WAIT signal in all AC Waveform Figures. Latch Enable
waveform modified in Figure 11, Asynchronous Page Read AC Waveforms.
VDDQ range split into two in Tables 20 and 21, Asynchronous and Synchronous Read
AC Characteristics: for VDDQ = 1.65V to 2.2V, tAVKH and tELKH in Table 20, and tLLKH
in Table 21, were changed; for VDDQ = 2.2V to 3.3V, tAVQV1, tELTV, tEHTZ, tEHQZ,
tGLQV, tAVLH, tLLH in Table 20 and all the timings in Table 21 were modified.
Data reserved at addresses 35h and 38h in Table 33, Device Geometry Definition.
Data corrected at address offset (P+37)h = 70h in Table 39, Bank and Erase Block
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