參數(shù)資料
型號(hào): M58WR064EBZB
廠商: 意法半導(dǎo)體
英文描述: 64 Mbit 4Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory
中文描述: 64兆位4Mb的× 16,多銀行,突發(fā)1.8V電源快閃記憶體
文件頁數(shù): 43/82頁
文件大?。?/td> 1100K
代理商: M58WR064EBZB
48/82
Table 23. Write AC Characteristics, Chip Enable Controlled
Note: 1. Sampled only, not 100% tested.
2. tWHEL has the values shown when reading in the targeted bank. System designers should take this into account and may insert a
software No-Op instruction to delay the first read in the same bank after issuing a command. If it is a Read Array operation in a
different bank tWHEL is 0ns.
Symbol
Alt
Parameter
M58WR064E
Unit
70
80
100
Chip
Enable
C
ontrol
led
Ti
mings
tAVAV
tWC
Address Valid to Next Address Valid
Min
70
80
100
ns
tAVEH
tWC
Address Valid to Chip Enable High
Min
45
50
ns
tAVLH
Address Valid to Latch Enable High
Min
9
10
ns
tDVEH
tDS
Data Valid to Write Enable High
Min
45
50
ns
tEHAX
tAH
Chip Enable High to Address Transition
Min
0
ns
tEHDX
tDH
Chip Enable High to Input Transition
Min
0
ns
tEHEL
tWPH
Chip Enable High to Chip Enable Low
Min
25
ns
tEHGL
Chip Enable High to Output Enable Low
Min
0
ns
tEHWH
tCH
Chip Enable High to Write Enable High
Min
0
ns
tELKV
Chip Enable Low to Clock Valid
Min
9
ns
tELEH
tWP
Chip Enable Low to Chip Enable High
Min
45
50
ns
tELLH
Chip Enable Low to Latch Enable High
Min
10
ns
tELQV
Chip Enable Low to Output Valid
Min
70
80
100
ns
tGHEL
Output Enable High to Chip Enable Low
Min
17
20
ns
tLHAX
Latch Enable High to Address Transition
Min
9
10
ns
tLLLH
Latch Enable Pulse Width
Min
9
10
ns
tWHEL
(2)
Write Enable High to Chip Enable Low
Min
25
ns
tWHQV
Write Enable High to Output Valid
Min
95
105
125
ns
tWLEL
tCS
Write Enable Low to Chip Enable Low
Min
0
ns
Prote
ction
Timin
gs
tEHVPL
Chip Enable High to VPP Low
Min
200
ns
tEHWPL
Chip Enable High to Write Protect Low
Min
200
ns
tQVVPL
Output (Status Register) Valid to VPP Low
Min
0
ns
tQVWPL
Output (Status Register) Valid to Write Protect
Low
Min
0
ns
tVPHEH
tVPS
VPP High to Chip Enable High
Min
200
ns
tWPHEH
Write Protect High to Chip Enable High
Min
200
ns
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