參數(shù)資料
型號： M58WR064EBZB
廠商： 意法半導(dǎo)體
英文描述： 64 Mbit 4Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory
中文描述： 64兆位4Mb的× 16，多銀行，突發(fā)1.8V電源快閃記憶體
文件頁數(shù)： 37/82頁
文件大?。?/td> 1100K
代理商： M58WR064EBZB
42/82
Figure 12. Synchronous Burst Read AC Waveforms
AI06980c
DQ0-DQ15
E
G
A0-A21
L
WAIT
K
(3)
VALID
ADDRESS
tLLLH
tAVLH
tGLQX
tAVKH
tLLKH
tELKH
tKHAX
tKHQX
tKHQV
NOT
VALID
Note
1
Note
2
Note
2
tKHTX
tKHTV
tEHQX
tEHQZ
tGHQX
tGHQZ
tKHTX
Hi-Z
VALID
Note
2
tELTV
tKHTV
tEHTZ
Address
Latch
X
Latency
Valid
Data
Flow
Boundary
Crossing
Valid
Data
Standby
Note
1.
The
n
umber
of
cloc
k
cycles
to
be
inser
ted
depends
on
the
X
latency
set
in
the
Burst
Configur
ation
Register
.
2.
The
W
AIT
signal
can
be
configured
to
be
activ
e
dur
ing
w
ait
state
or
one
cycle
bef
ore
.W
AIT
signal
is
activ
e
Lo
w
.
3.
Address
latched
and
data
output
on
the
r
ising
cloc
k
edge
.Either
the
f
alling
or
the
r
ising
edge
of
the
cloc
k
signal
,K,
can
be
configured
as
the
activ
e
edge
.
Here
the
activ
e
edge
of
K
is
the
r
ising
one
.
tEHEL
tKHQV
tKHQX
tKHQV
tKHQX
Hi-Z
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