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參數(shù)資料
| 型號： | LC73101C |
| 文件頁數(shù)： | 7/34頁 |
| 文件大小： | 217K |
| 代理商： | LC73101C |
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Chip select
The LC73101C has two chip select inputs: CS1 and CS2. The microcontroller and the serial interface can only be used
when CS1 is low and CS2 is high. When the chip select inputs select a non-active state, the D0 to D7 pins go to the
high-impedance state and the A0, RD, and WR inputs are disabled. The serial interface shift register and counter are
reset.
Access to display data RAM and internal registers
The LC73101C supports high-speed data transfers that require no wait time as long as the LC73101C access cycle time
constraints are met by the microcontroller. The LC73101C uses an internal “bus holder” circuit on its internal data bus
to receive or send data during data transfers with the microcontroller.
For example, when the microcontroller writes to LC73101C display data RAM, the data is temporarily held by the bus
holder and written to the display data RAM before the next write cycle. When the microcontroller reads out the
contents of the display data RAM, data read out on the first (dummy) read cycle is stored in the bus holder, and then
that data is read out onto the system bus on the next data read cycle. When reading display data RAM, after setting the
address, the immediately following read instruction does not read out the data at the address specified, but rather reads
out the data from the address specified by the second preceding data read operation. Thus care is required when using
this function. This means that one dummy read operation is always required after setting the address or after a write
cycle. Figure 2 (a) and figure 2 (b) show this timing.
Busy flag
When the busy flag is high, it indicates that an LC73101C internal operation is in progress.
The busy flag is output from the D7 pin by a Status Read command. If the cycle time (t
CYC
) conditions are met, there
is no need to check this flag before each command. This can significantly increase the available processing power of
the microcontroller.
No. 6853-7/34
LC73101C
(a) Read
N
WR
RD
DATA
N
Address N
N+1
N+2
Address Preset
Read Signal
Column Address
Bus Holder
M
I
Unknown
Data N
Data N+1
Address Set
Dummy
Read
Data Read
N+1
Data Read
N
WR
DATA
N+1
N+2
N+3
N
N+1
N+2
N+3
BUS Holder
RAM Write Signal
M
I
t
(a) Write
Latch
Data Write Complete
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