
No. 6853-32/34
LC73101C
Serial Interface
Figure 12
t
CSS
SCL
CS1
(CS2 = “1”)
t
SHW
t
r
t
SDH
t
SDS
t
f
t
SLW
t
SCYC
t
SAH
t
SAS
t
CSH
A0
SI
Parameter
Signal
Symbol
Conditions
Ratings
Unit
min
max
Serial clock period
t
SCYC
t
SHW
t
SLW
t
SAS
t
SAH
t
SDS
t
SDH
t
CSS
t
CSH
250
—
SCL high-level pulse width
SCL
100
—
ns
SCL low-level pulse width
100
—
Address setup time
A0
150
—
ns
Address hold time
150
—
Data setup time
SI
100
—
ns
Data hold time
100
—
CS to CSL time
CS
150
—
ns
150
—
V
DD
= 2.7 to 3.6 V, Ta = –40 to 85°C
Parameter
Signal
Symbol
Conditions
Ratings
Unit
min
max
Serial clock period
t
SCYC
t
SHW
t
SLW
t
SAS
t
SAH
t
SDS
t
SDH
t
CSS
t
CSH
400
—
SCL high-level pulse width
SCL
150
—
ns
SCL low-level pulse width
150
—
Address setup time
A0
250
—
ns
Address hold time
250
—
Data setup time
SI
150
—
ns
Data hold time
150
—
CS to CSL time
CS
250
—
ns
250
—
V
DD
= 1.8 to 2.7 V, Ta = –40 to 85°C
Notes: 1. The input signal rise and fall times (t
r
, t
f
) are stipulated to be under 15 ns.
2. All timings are stipulated to be referenced to 20% and 80% of V
DD
.