
Partial Display Function
Partial display function
The LC73101C provides commands that control the following settings: the LCD drive duty setting, the LCD drive bias
selection, the number of stages of voltage step-up, the display start line address, and the display start common address.
These settings can be used to only display part of the screen.
The number of lines displayed by the partial display function can be selected to be 8, 16, 24, 32, 40, 48, 56, 64, 72, or
80 lines. This is set by setting the LCD duty. The start of the frame is the display start line, and by setting this line to be
the display start common address, it is possible to select any of the COM0 to COM79 lines.
In general, as the LCD drive duty is reduced, the optimal values of the LCD drive voltage and LCD drive bias also
become smaller. Since this allows the number of step-up stages in the voltage step-up circuit to be reduced, power
consumption can be reduced significantly.
Duty and frame frequency
Table 4 shows the relationship between the duty setting, the number of lines, the display clock frequency f
CL
, and the
frame frequency f
FR
.
Oscillator Circuit
This circuit is an RC circuit that generates the display clock. The oscillator circuit is only enabled when M/S is high and
CLS is high. When CLS is low, the oscillator circuit is stopped and the display clock is input to the CL pin.
No. 6853-11/34
LC73101C
Table 4
Duty
Number of lines
displayed
f
CL
[kHz]
f
FR
[Hz]
80
80
6.40
80.0
72
72
5.12
71.1
64
64
5.12
80.0
56
56
4.27
76.2
48
48
3.66
76.2
40
40
3.20
80.0
32
32
2.56
80.0
24
24
1.97
82.1
16
16
1.28
80.0
8
8
0.640
80.0