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參數(shù)資料
| 型號(hào)： | LC73101C |
| 文件頁數(shù)： | 6/34頁 |
| 文件大?。?/td> | 217K |
| 代理商： | LC73101C |
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Functional Description
Microcontroller Interface
Interface type selection
The LC73101C transfers data over either an 8-bit bidirectional data bus (D0 to D7) or a serial data input system (SI).
Applications can select either 8-bit parallel data input or serial data input as shown in table 1 by setting the P/S pin
either high or low.
Parallel interface
When the parallel interface is selected (P/S = high), the bus of either an Intel-type or a Motorola-type microcontroller
can be directly connected to the LC73101C parallel interface by setting the C86 pin either high or low as shown in
table 2.
Serial interface
When the serial interface is selected (P/S = low), data can be written to the LC73101C using the serial input (SI) and
serial clock (SCL) pins with the chip in the active state (CS1 = low, CS2 = high). The serial interface consists of an 8-
bit shift register and a 3-bit counter. Serial data is acquired from the serial data input pin in the order D7 to D0 on the
rising edge of the serial clock signal. The serial data is converted to 8 bits of parallel data on the eighth rising edge of
the serial clock and processed by the LC73101C.
Whether the serial data input is display data or a command is determined by the state of the A0 input. When A0 is high,
the data is display data, and when A0 is low, it is taken to be a command. The A0 input is acquired and interpreted
once every eight rising edges (that is, on the 8
×
th rising edge) of the serial clock signal after the chip goes to the active
state.
Figure 1 shows the timing chart for the serial interface.
When the chip is in a non-active state due to the CS1 and CS2 inputs, the shift register and the counter are reset. The
serial interface does not support readout. Be sure to prevent termination reflections and noise from appearing on the
SCL signal. We recommend testing in an actual end product.
No. 6853-6/34
LC73101C
Table 1
P/S
CS1
CS2
A0
RD
WR
C86
D7
D6
D5 to D0
High: Parallel input
CS1
CS2
A0
RD
WR
C86
D7
D6
D5 to D0
Low: Serial input
CS1
CS2
A0
—
—
—
SI
SCL
High impedance
Table 2
C86
CS1
CS2
A0
RD
WR
D7 to D0
High: Mptorola-type MPU bus
CS1
CS2
A0
E
R/W
D7 to D0
Low: Intel-type MPU bus
CS1
CS2
A0
RD
WR
D7 to D0
SCL(D6)
SI(D7)
CS1
ParallelData
(InternalDataBus)
CS2
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D7:0
00H
X
XXH
Data or
XX
00H
P/S
Figure 1
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