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參數(shù)資料
| 型號(hào)： | LC73101C |
| 文件頁數(shù)： | 12/34頁 |
| 文件大?。?/td> | 217K |
| 代理商： | LC73101C |
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Display Timing Generator
This circuit generates the timing signals for the line address circuit and the display data latch circuit from the display
clock. The display data is latched by the display data latch circuit in synchronization with the display clock and output to
the segment drive output pins. Readout of the display data to the LCD drive circuit is completely independent of
microcontroller access to the display data RAM. This means that flicker or other problems never occur due to the display
RAM being accessed asynchronously during display on the LCD panel. This circuit also generates the internal common
timing and the LCD alternation signal (FR) from the display clock. The two-frame alternation drive waveforms shown in
figure 5 are generated for the LCD drive circuit.
Figure 5 Frame Alternation Drive Waveforms
When the LC73101C is used in a multi-chip configuration, the display timing signals (FR, CL, and DOF) must be
provided to the slave by the master.
Table 5 shows the states of the FR, CL, and DOF pins.
No. 6853-12/34
LC73101C
CL
79 80
1
2
3
4
5
6
COM0
FR
COM1
V
1
V
2
V
1
V
2
V
5
V
SS
V
5
V
SS
V
1
V
3
V
4
V
SS
RAM
DATA
SEGn
75 76 77 78 79 80
1
2
3
4
5
6
Table 5
Setting
FR
CL
DOF
M/S
CLS
“H”
“H”
Output
Output
Output
“L”
Output
Input
Output
“L”
“H” or “L”
Input
Input
Input
“H” or “L”
Input
Input
Input
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