- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369722 > LC73101C PDF資料下載
參數(shù)資料
| 型號： | LC73101C |
| 文件頁數(shù)： | 30/34頁 |
| 文件大?。?/td> | 217K |
| 代理商： | LC73101C |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁第32頁第33頁第34頁
AC Characteristics
System Bus Read/Write Characteristics (1) (Intel-type microcontrollers)
Figure 10
No. 6853-30/34
LC73101C
A0
t
AW8
t
DS8
t
AH8
t
DS8
t
ACC8
t
OH8
t
CCHR
,t
CCH
t
CCLR
,t
CCLW
t
CYC8
CS1
(CS2 = “1”)
WR, RD
D0 to D7
(Write)
D0 to D7
(Read)
Parameter
Signal
Symbol
Conditions
Ratings
Unit
min
max
Address hold time
A0
t
AH8
T
AW8
t
CYC8
t
CCLW
t
CCLR
t
CCHW
t
CCHR
t
DS8
t
DH8
t
ACC8
t
OH8
0
—
ns
Address setup time
0
—
System cycle time
A0
300
—
ns
Control low-level pulse width (WR)
WR
60
—
Control low-level pulse width (RD)
RD
120
—
ns
Control high-level pulse width (WR)
WR
60
—
Control high-level pulse width (RD)
RD
60
—
Data setup time
D0 to D7
40
—
ns
Address hold time
15
—
RD access time
D0 to D7
C
L
= 100 pF
—
140
ns
Output disable time
10
100
V
DD
= 2.7 to 3.6 V, Ta = –40 to 85°C
Parameter
Signal
Symbol
Conditions
Ratings
Unit
min
max
Address hold time
A0
t
AH8
T
AW8
t
CYC8
t
CCLW
t
CCLR
t
CCHW
t
CCHR
t
DS8
t
DH8
t
ACC8
t
OH8
0
—
ns
Address setup time
0
—
System cycle time
A0
1000
—
ns
Control low-level pulse width (WR)
WR
120
—
Control low-level pulse width (RD)
RD
240
—
ns
Control high-level pulse width (WR)
WR
120
—
Control high-level pulse width (RD)
RD
120
—
Data setup time
D0 to D7
80
—
ns
Address hold time
30
—
RD access time
D0 to D7
C
L
= 100 pF
—
280
ns
Output disable time
10
200
V
DD
= 1.8 to 2.7 V, Ta = –40 to 85°C
Notes: 1. The input signal rise and fall times (t
r
, t
f
) are stipulated to be under 15 ns. When using a short system cycle time for high-speed operation, these are
stipulated as follows: (t
r
+ t
f
)
≤
(t
CYC8
- t
CCLW
- t
CCHW
) or (t
r
+ t
f
)
≤
(t
CYC8
- t
CCLR
- t
CCHR
)
2. All timings are stipulated to be referenced to 20% and 80% of V
DD
.
3. t
CCLW
and t
CCLR
are stipulated to be the overlap time when CS1 is low (CS2 is high) and WR and RD are low.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LC7350 | Telecommunication IC |
| LC7351 | |
| LC7352 | Telecommunication IC |
| LC7353 | |
| LC7354 | Telecommunication IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC73-17 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Laser Diode with Monitor Diode |
| LC7350 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| LC7351 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| LC7352 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| LC7353 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。