參數(shù)資料
型號(hào)： LC73101C
文件頁(yè)數(shù)： 21/34頁(yè)
文件大?。?/td> 217K
代理商： LC73101C
5. Column Address Set
Sets the column address for display data RAM. This address is set in two operations: first the upper 4 bits and then the
lower 4 bits. The column address is automatically incremented (+1) each time display data RAM is accessed. Thus there
is no need to issue this command each time this RAM is read or written, and the microcontroller can read or write display
data consecutively.
Automatic increment of the column address stops when it reaches 83H.
See the functional description in the "Column Address Circuit" section for details.
6. Status Read
Allows the microcontroller to read out the IC state from the status data.
7. Display Data Write
Writes 8 bits of data to the address specified for display data RAM. After the write, the column address is automatically
incremented to allow the microcontroller to write display data continuously.
No. 6853-21/34
LC73101C
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
0
1
M7
M6
M5
M4
0
0
0
0
M3
M2
M1
M0
M6
M5
M4
M3
M2
M1
M0
Column Start Address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
↓
0
0
1
0
2
↓
1
0
0
0
1
0
130
1
0
0
0
0
1
1
131
Busy flag
ST1
When ST1 is 1, indicates that either a read operation or an internal operation is in progress.
This command can be issued until ST1 becomes 0. However, there is no need to check this flag if the cycle time conditions are met.
Indicates the correspondence between column addresses and segment drivers.
0: Inverted (Column addresses 0H
→
83H: SEG0
→
SEG131)
1: Normal (Column addresses 0H
→
83H: SEG131
→
SEG0)
Indicates the on/off state of the display. (This value has the reverse polarity of the Display On/Off command.)
ST2
ST3
0: Display on
1: Display off
Indicates that an initialization operation due to either the RES signal or a Reset command.
ST4
0: Operating state
1: Reset in progress
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
ST4
ST3
ST2
ST1
1
1
1
1
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
Write data
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