參數(shù)資料
型號(hào)： LC73101C
文件頁(yè)數(shù)： 4/34頁(yè)
文件大?。?/td> 217K
代理商： LC73101C
No. 6853-4/34
LC73101C
System Bus Connection Pins
Pin
I/O
Function
Number of pins
Bidirectional 8-bit data bus connected to the microcontroller data bus.
When the serial interface is selected (P/S is low):
D7: Serial data input (SI)
D6: Serial clock input (SCL)
In this mode, D0 to D5 go to the high-impedance state. When the chip select line is inactive, D0 to D7 go to the
high-impedance state.
D0 to D7
I/O
8
A0 is normally connected to the low order bit of the microcontroller address bus and discriminates between data
and commands.
A0 = high: Indicates that D0 to D7 are used for data display.
A0 = low: Indicates that D0 to D7 are used for control data.
A0
I
1
RES
I
The LC73101C is initialized when RES is set low.
The reset operation is performed by the RES signal level.
1
CS1
CS2
I
Chip select signals. The LC73101C becomes active when CS1 is low and CS2 is high. Input and output of data
and commands is possible in this state.
2
This pin is active-low when an Intel-type microcontroller is used.
The Intel-type microcontroller RD signal should be connected to this pin. The LC73101C data bus goes to the
output state when this signal is low.
This pin is active-high when a Motorola-type microcontroller is used.
This pin functions as the enable clock input pin when a Motorola-type microcontroller is used.
RD
(E)
I
1
This pin is active-low when an Intel-type microcontroller is used.
The Intel-type microcontroller WR signal should be connected to this pin. The data bus signals are latched on the
rising edge of the WR signal.
When a Motorola-type microcontroller is used:
This pin functions as the read/write control signal input.
R/W = high: Read, R/W = low: Write.
WR
(R/W)
I
C86 is the Microcontroller interface switching input.
C86 = high: Motorola-type interface
C86 = low: Intel-type interface
C86
I
1
Parallel/serial data input mode switch
P/S = high: Parallel input
P/S = low: Serial input
The table below lists the effects of this pin.
P/S
I
1
When P/S is low, D0 to D5 go to the high-impedance state.
D0 to D5 may be left high, low, or open in this mode.
RD (E) and WR (R/W) must be held either high or low.
In serial data input mode, the RAM display data and the device status cannot be read.
Selects enabled/disabled for the internal oscillator circuit for display clock
1
CLS
I
CLS = high: Internal oscillator circuit enabled.
CLS = low: Internal oscillator circuit disabled. (External input)
If CLS is low, input the display clock signal to the CL pin.
Selects master or slave mode operation for the LC73101C itself.
In slave mode operation, synchronization with the display system is acquired by input of the timing signals
required for LCD display.
M/S = high: Master operation
M/S = low: Slave operation
M/S
I
The M/S and CLS pins determine the operating state as shown in the table below.
1
P/S
Data/command
Data
Read/write
Serial clock
“H”
A0
D0 to D7
RD, WR
—
“L”
A0
SI (D7)
Write only
SCL (D6)
M/S
CLS
Oscillator circuit
Power supply circuit
CL
FR
DOF
“H”
“H”
Enabled
Enabled
Output
Output
Output
“L”
Disabled
Enabled
Input
Output
Output
“L”
“H”
Disabled
Disabled
Input
Input
Input
“L”
Disabled
Disabled
Input
Input
Input
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