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| 型號： | LC73101C |
| 文件頁數(shù)： | 31/34頁 |
| 文件大?。?/td> | 217K |
| 代理商： | LC73101C |
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No. 6853-31/34
LC73101C
System Bus Read/Write Characteristics (2) (Motorola-type microcontrollers)
Figure 11
A0
R/W
t
AW6
t
DS6
t
AH6
t
DS6
t
ACC6
t
OH6
t
EWLR
,t
EWLW
t
EWHR
,t
EWHW
t
CYC
CS1
(CS2 = “1”)
E
D0 to D7
(Write)
D0 to D7
(Read)
Parameter
Signal
Symbol
Conditions
Ratings
Unit
min
max
Address hold time
A0
t
AH6
T
AW6
t
CYC6
t
DS6
t
DH6
t
ACC6
t
OH6
t
EWHR
t
EWHW
t
EWLR
t
EWLW
0
—
ns
Address setup time
0
—
System cycle time
A0
300
—
ns
Data setup time
D0 to D7
40
—
ns
Address hold time
15
—
Access time
D0 to D7
C
L
= 100 pF
—
140
ns
Output disable time
10
100
Enable high-level pulse width
Read
E
120
—
ns
Write
60
—
Enable low-level pulse width
Read
E
60
—
ns
Write
60
—
V
DD
= 2.7 to 3.6 V, Ta = –40 to 85°C
Parameter
Signal
Symbol
Conditions
Ratings
Unit
min
max
Address hold time
A0
t
AH6
T
AW6
t
CYC6
t
DS6
t
DH6
t
ACC6
t
OH6
t
EWHR
t
EWHW
t
EWLR
t
EWLW
0
—
ns
Address setup time
0
—
System cycle time
A0
1000
—
ns
Data setup time
D0 to D7
80
—
ns
Address hold time
30
—
Access time
D0 to D7
C
L
= 100 pF
—
280
ns
Output disable time
10
200
Enable high-level pulse width
Read
D0 to D7
240
—
ns
Write
120
—
Enable low-level pulse width
Read
D0 to D7
120
—
ns
Write
120
—
V
DD
= 1.8 to 2.7 V, Ta = –40 to 85°C
Notes: 1. The input signal rise and fall times (t
r
, t
f
) are stipulated to be under 15 ns. When using a short system cycle time for high-speed operation, these are
stipulated as follows: (t
r
+ t
f
)
≤
(t
CYC6
- t
EWLW
- t
EWHW
) or (t
r
+ t
f
)
≤
(t
CYC6
- t
EWLR
- t
EWHR
)
2. All timings are stipulated to be referenced to 20% and 80% of V
DD
.
3. t
EWLW
and t
EWLR
are stipulated to be the overlap time when CS1 is low (CS2 is high) and E is low.
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