參數(shù)資料
型號(hào): K9F4G08U0M
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 512M x 8 Bits / 1G x 8 Bits NAND Flash Memory
中文描述: 512M x 8位/ 1克× 8位NAND閃存
文件頁數(shù): 31/41頁
文件大?。?/td> 1076K
代理商: K9F4G08U0M
FLASH MEMORY
31
Advance
K9F4G08U0M
K9K8G08U1M
Device Operation
PAGE READ
Read mode is initiated by writing 00h-30h to the command register along with five address cycles. In two consecutive read opera-
tions, the second one doesn’t need 00h command, which five address cycles and 30h command initiates that operation. Once the
command is latched, it does not need to be written for the following page read operation. Two types of operations are available : ran-
dom read out, serial page read out.
The random read mode is enabled when the page address is changed. The 2,112 bytes of data within the selected page are trans-
ferred to the data registers in less than 20
μ
s(t
R
). The system controller can detect the completion of this data transfer(tR) by analyzing
the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 25ns cycle time by sequen-
tially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the selected col-
umn address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data output command.
The column address of next data, which is going to be out, may be changed to the address which follows random data output com-
mand. Random data output can be operated multiple times regardless of how many times it is done in a page.
Figure 6. Read Operation
Address(5Cycle)
00h
Col. Add.1,2 & Row Add.1,2,3
Data Output(Serial Access)
Data Field
Spare Field
CE
CLE
ALE
R/B
WE
RE
t
R
30h
I/Ox
相關(guān)PDF資料
PDF描述
K9K8G08U1M 512M x 8 Bits / 1G x 8 Bits NAND Flash Memory
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K9F5608Q0C-H 512Mb/256Mb 1.8V NAND Flash Errata
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