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參數資料
| 型號： | K4N56163QF |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Mbit gDDR2 SDRAM |
| 中文描述： | 片256Mbit GDDR2 SDRAM的 |
| 文件頁數： | 43/73頁 |
| 文件大?。?/td> | 1262K |
| 代理商： | K4N56163QF |
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- 43 -
Rev 1.6 (Apr. 2005)
256M gDDR2 SDRAM
K4N56163QF-GC
Burst Write Operation
The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the
clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL)
minus one and is equal to (AL + CL -1). A data strobe signal (DQS) should be driven low (preamble) one clock prior to the
WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the
preamble. The tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on succes-
sive edges of the DQS until the burst length is completed, which is 4 or 8 bit burst. When the burst has finished, any addi-
tional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is complete.
The time from the completion of the burst write to bank precharge is the write recovery time (WR).
gDDR2 SDRAM pin timings are specified for either single ended mode or differen-tial mode depending on the setting of
the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by
which the gDDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are
measured relative to the rising or falling edges of DQS crossing at V
REF
. In differential mode, these timing relationships are
measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by
design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary
pin, DQS, must be tied externally to VSS through a 20 ohm to 10K ohm resistor to insure proper operation.
Burst Write Operation: RL = 5, WL = 4, tWR = 3 (AL=2, CL=3), BL = 4
t
DS
t
DS
t
DH
t
WPRE
t
WPST
t
DQSH
t
DQSL
DQS
DQS
D
DMin
DQS/
DQS
DQ
DM
t
DH
DMin
IL
(ac)
DMin
DMin
IL
(dc)
D
D
D
V
IL
(ac)
V
IH
(ac)
V
IH
(ac)
V
IL
(dc)
V
IH
(dc)
V
IH
(dc)
CMD
NOP
NOP
NOP
NOP
NOP
NOP
DQs
NOP
CK/CK
T0
T2
T1
T3
T4
T5
T6
T7
Tn
WRITE A
Posted CAS
WL = RL - 1 = 4
DQS
< = t
DQSS
> = WR
DIN A
0
DIN A
1
DIN A
2
DIN A
3
Precharge
Completion of
the Burst Write
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相關代理商/技術參數 |
參數描述 |
|---|---|
| K4N56163QF-GC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit gDDR2 SDRAM |
| K4N56163QF-GC25 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit gDDR2 SDRAM |
| K4N56163QF-GC30 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit gDDR2 SDRAM |
| K4N56163QF-GC37 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit gDDR2 SDRAM |
| K4N56163QG-ZC2A | 制造商:Samsung Semiconductor 功能描述: |
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