參數(shù)資料
型號: K4N56163QF
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 256Mbit gDDR2 SDRAM
中文描述: 片256Mbit GDDR2 SDRAM的
文件頁數(shù): 31/73頁
文件大?。?/td> 1262K
代理商: K4N56163QF
- 31 -
Rev 1.6 (Apr. 2005)
256M gDDR2 SDRAM
K4N56163QF-GC
ODT (On Die Termination)
On Die Termination (ODT) is a feature that allows a DRAM to turn on/off termination resistance. For x16 configuration
ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal via the ODT control pin. The ODT feature
is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off
termination resistance for any or all DRAM devices.
The ODT function is supported for ACTIVE and STANDBY modes, and turned off and not supported in SELF REFRESH
mode.
Functional Representation of ODT
ODT DC Electrical Characteristics
Note 1: Test condition for Rtt measurements
Measurement Definition for Rtt(eff):
Apply V
IH
(AC) and V
IL
(AC) to test pin separately, then measure current I(V
IH
(AC)) and I(
V
IL
(AC))
respectively. V
IH
(AC)
,
V
IL
(AC)
, and VDDQ values defined in SSTL_18
Measurement Definition for VM:
Measure voltage (V
M
) at test pin (midpoint) with no load.
Parameter/Condition
Symbol
Rtt1(eff)
Rtt2(eff)
Rtt(mis)
Min
60
120
-3.75
Nom
75
150
Max
90
180
+3.75
Units
ohm
ohm
%
Notes
1
1
1
Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 ohm
Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 ohm
Rtt mismatch tolerance between any pull-up/pull-down pair
Input
Pin
DRAM
Input
Buffer
V
SS
Q
V
SS
Q
V
DD
Q
V
DD
Q
Rval2
Rval2
Rval1
Rval1
sw1
sw1
sw2
sw2
Selection between sw1 or sw2 is determined by “
R
tt (nominal)” in EMRS
Termination included on all DQs, DM, DQS and
DQS
pins.
Target
R
tt
(
ohm)
=
(Rval1) / 2 or (Rval2) / 2
Switch sw1 or sw2 is enabled by ODT pin.
Rtt(eff) =
V
IH
(AC)
-
V
IL
(AC)
I(
V
IH
(AC)
) - I(
V
IL
(AC)
)
delta VM =
2 x Vm
VDDQ
x 100%
- 1
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