參數(shù)資料
型號(hào): K4N56163QF
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 256Mbit gDDR2 SDRAM
中文描述: 片256Mbit GDDR2 SDRAM的
文件頁(yè)數(shù): 23/73頁(yè)
文件大?。?/td> 1262K
代理商: K4N56163QF
- 23 -
Rev 1.6 (Apr. 2005)
256M gDDR2 SDRAM
K4N56163QF-GC
1. Calibration Mode Exit command (A9=A8=A7=0) must be issued with other operating parameters of EMRS.
2. The gDDR2 SDRAM is now ready for normal operation.
*1) To guarantee ODT off, V
REF
must be valid and a low level must be applied to the ODT pin.
Programming the Mode Register
For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time(tWR) are user
defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable func-
tion, driver impedance, additive CAS latency, ODT(On Die Termination), single-ended strobe, and OCD(off chip driver
impedance adjustment) are also user defined variables and must be programmed with an Extended Mode Register Set
(EMRS) command. Contents of the Mode Register(MR) or Extended Mode Registers(EMR(#)) can be altered by re-exe-
cuting the MRS and EMRS Commands. If the user chooses to modify only a subset of the MRS or EMRS variables, all
variables must be redefined when the MRS or EMRS commands are issued.
MRS, EMRS and Reset DLL do not affect array contents, which means reinitialization including those can be executed
any time after power-up without affecting array contents.
Initialization Sequence after Power Up
/CK
CK
CKE
Command
PRE
ALL
PRE
ALL
EMRS
MRS
REF
REF
MRS
EMRS
EMRS
ANY
CMD
DLL
ENABLE
DLL
RESET
OCD
Default
OCD
CAL. MODE
EXIT
Follow OCD
Flowchart
400ns
tRFC
tRFC
tRP
tRP
tMRD
tMRD
tMRD
tOIT
min. 200 Cycle
NOP
ODT
tCL
tCH
tIS
V
IH(ac)
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