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參數(shù)資料
| 型號： | K4N56163QF |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Mbit gDDR2 SDRAM |
| 中文描述： | 片256Mbit GDDR2 SDRAM的 |
| 文件頁數(shù)： | 3/73頁 |
| 文件大?。?/td> | 1262K |
| 代理商： | K4N56163QF |
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- 3 -
Rev 1.6 (Apr. 2005)
256M gDDR2 SDRAM
K4N56163QF-GC
4M x 16Bit x 4 Banks graphic DDR2 Synchronous DRAM
with Differential Data Strobe
1.8V + 0.1V power supply for device operation
1.8V + 0.1V power supply for I/O interface
4 Banks operation
Posted CAS
Programmable CAS Letency : 4, 5, 6 and 7
Programmable Additive Latency : 0, 1, 2, 3, 4 and 5
Write Latency (WL) = Read Latency (RL) -1
Burst Legth : 4 and 8 (Interleave/nibble sequential)
Programmable Sequential/ Interleave Burst Mode
GENERAL DESCRIPTION
FOR 4M x 16Bit x 4 Bank gDDR2 SDRAM
FEATURES
Bi-directional Differential Data-Strobe
(Single-ended data-strobe is an optional feature)
Off-chip Driver (OCD) Impedance Adjustment
On Die Termination
Refresh and Self Refresh
Average Refesh Period 7.8us at lower then T
CASE
85×C,
3.9us at 85×C < T
CASE
< 95 ×C
84 ball FBGA
ORDERING INFORMATION
* K4N56163QF-ZC is the Lead-Free part number.
Part NO.
Max Freq.
Max Data Rate
Interface
Package
K4N56163QF-GC25
400MHz
800Mbps/pin
SSTL
84 Ball FBGA
K4N56163QF-GC30
333MHz
667Mbps/pin
K4N56163QF-GC37
266MHz
533Mbps/pin
The 256Mb gDDR2 SDRAM chip is organized as 4Mbit x 16 I/O x 4banks banks device. This synchronous device
achieve high speed graphic double-data-rate transfer rates of up to 1000Mb/sec/pin for general applications. The chip is
designed to comply with the following key gDDR2 SDRAM features such as posted CAS with additive latency, write latency
= read latency - 1, Off-Chip Driver(OCD) impedance adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirec-
tional strobes (DQS and DQS) in a source synchronous fashion. A thirteen bit address bus is used to convey row, column,
and bank address information in a RAS/CAS multiplexing style. For example, 256Mb(x16) device receive 13/9/2 address-
ing. The 256Mb gDDR2 devices operate with a single 1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ.
The 256Mb gDDR2 devices are available in 84ball FBGAs(x16).
Note : The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of
operation.
相關PDF資料 |
PDF描述 |
|---|---|
| K4N56163QF-GC | 256Mbit gDDR2 SDRAM |
| K4N56163QF-GC25 | 256Mbit gDDR2 SDRAM |
| K4N56163QF-GC30 | 256Mbit gDDR2 SDRAM |
| K4N56163QF-GC37 | 256Mbit gDDR2 SDRAM |
| K4PE68A | Transient Voltage Suppressor Diodes |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| K4N56163QF-GC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit gDDR2 SDRAM |
| K4N56163QF-GC25 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit gDDR2 SDRAM |
| K4N56163QF-GC30 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit gDDR2 SDRAM |
| K4N56163QF-GC37 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit gDDR2 SDRAM |
| K4N56163QG-ZC2A | 制造商:Samsung Semiconductor 功能描述: |
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