參數(shù)資料
型號(hào)： K4J52324KI-HC1A0
元件分類： DRAM
英文描述： 512M X 1 DDR DRAM, 0.2 ns, PBGA136
封裝： HALOGEN FREE AND ROHS COMPLIANT, FBGA-136
文件頁(yè)數(shù)： 8/61頁(yè)
文件大小： 1364K
代理商： K4J52324KI-HC1A0
- 16 -
K4J52324KI
datasheet
GDDR3 SGRAM
Rev. 1.2
DLL ENABLE/DISABLE
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after dis-
abling the DLL for debugging or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled,
20K clock cycles must occur before a READ command can be issued.
DATA TERMINATION
The Data Termination, DT, is used to determine the value of the internal data termination resisters. The GDDR3 SGRAM supports 60
Ω and 120Ω termi-
nation. The termination may also be disabled for testing and other purposes.
DATA DRIVER IMPEDANCE
The Data Driver impedance (DZ) is used to determine the value of the data drivers impedance. When autocalibration is used the data driver impedance
is set to RQ/6 and it’s tolerance is determined by the calibration accuracy of the device. When any other value is selected the target impedance is set
nominally to the desired impedance. However, the accuracy is now determined by the device’s specific process corner, applied voltage and operating
temperature.
MANUFACTURERS VENDOR CODE AND REVISION IDENTIFICATION
The Manufacturers Vendor Code, V, is selected by issuing a EXTENDED MODE REGISTER SET command with bits A10 set to one, and bits A0-A9 and
A11 set to the desired values. When the V function is enabled the GDDR3 SGRAM will provide its manufacturers vendor code on DQ[3:0] and revision
identification on DQ[7:4]
Manufacturer
DQ[7:4]
DQ[3:0]
Samsung
2[0010]
1[0001]
DQs
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Vendor ID
0
1
0
1
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